From owner-svn-src-all@FreeBSD.ORG Wed May 14 17:01:36 2014 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 2381BCBB; Wed, 14 May 2014 17:01:36 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 05E5023C1; Wed, 14 May 2014 17:01:36 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s4EH1ZwS037432; Wed, 14 May 2014 17:01:35 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s4EH1ZaV037429; Wed, 14 May 2014 17:01:35 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201405141701.s4EH1ZaV037429@svn.freebsd.org> From: Ian Lepore Date: Wed, 14 May 2014 17:01:35 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r266050 - in stable/10/sys/arm: arm include X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 May 2014 17:01:36 -0000 Author: ian Date: Wed May 14 17:01:35 2014 New Revision: 266050 URL: http://svnweb.freebsd.org/changeset/base/266050 Log: MFC r256707, r256708, r257291, r258358 Switch to use WBWA mappings for page tables on armv6, this is needed for SMP. Fix PTE_SYNC() for PIPT L2 caches, using the virtual address wasn't so useful. Use PTE_SYNC() for >= armv6 Spell cpu_l2cache_wb_range correctly. Fix condition that determines PMAP_NEEDS_PTE_SYNC value for ARM Use values of the correct defines to determine statement's result. ARM_ARCH_ symbols are always defined, hence only values are relevant. Avoid clearing EXEC permission bit when setting the page RW on ARMv6/v7 When emulating modified bit the executable attribute was cleared by mistake when calling pmap_set_prot(). Modified: stable/10/sys/arm/arm/cpufunc_asm_armv7.S stable/10/sys/arm/arm/pmap-v6.c stable/10/sys/arm/include/pmap.h Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/arm/arm/cpufunc_asm_armv7.S ============================================================================== --- stable/10/sys/arm/arm/cpufunc_asm_armv7.S Wed May 14 17:01:31 2014 (r266049) +++ stable/10/sys/arm/arm/cpufunc_asm_armv7.S Wed May 14 17:01:35 2014 (r266050) @@ -57,9 +57,9 @@ __FBSDID("$FreeBSD$"); #define PT_OUTER_WBWA (1 << 3) #ifdef SMP -#define PT_ATTR (PT_S|PT_INNER_WT|PT_OUTER_WT|PT_NOS) +#define PT_ATTR (PT_S|PT_INNER_WBWA|PT_OUTER_WBWA|PT_NOS) #else -#define PT_ATTR (PT_INNER_WT|PT_OUTER_WT) +#define PT_ATTR (PT_INNER_WBWA|PT_OUTER_WBWA) #endif ENTRY(armv7_setttb) @@ -98,7 +98,7 @@ ENTRY(armv7_tlb_flushID_SE) ldr r1, .Lpage_mask bic r0, r0, r1 #ifdef SMP - mcr p15, 0, r0, c8, c3, 1 /* flush D tlb single entry Inner Shareable*/ + mcr p15, 0, r0, c8, c3, 3 /* flush D tlb single entry Inner Shareable*/ mcr p15, 0, r0, c7, c1, 6 /* flush BTB Inner Shareable */ #else mcr p15, 0, r0, c8, c7, 1 /* flush D tlb single entry */ Modified: stable/10/sys/arm/arm/pmap-v6.c ============================================================================== --- stable/10/sys/arm/arm/pmap-v6.c Wed May 14 17:01:31 2014 (r266049) +++ stable/10/sys/arm/arm/pmap-v6.c Wed May 14 17:01:35 2014 (r266050) @@ -1519,10 +1519,10 @@ pmap_fault_fixup(pmap_t pmap, vm_offset_ vm_page_dirty(m); /* Re-enable write permissions for the page */ - pmap_set_prot(ptep, VM_PROT_WRITE, *ptep & L2_S_PROT_U); - CTR1(KTR_PMAP, "pmap_fault_fix: new pte:0x%x", pte); + *ptep = (pte & ~L2_APX); PTE_SYNC(ptep); rv = 1; + CTR1(KTR_PMAP, "pmap_fault_fix: new pte:0x%x", *ptep); } else if (!L2_S_REFERENCED(pte)) { /* * This looks like a good candidate for "page referenced" @@ -1545,6 +1545,7 @@ pmap_fault_fixup(pmap_t pmap, vm_offset_ *ptep = pte | L2_S_REF; PTE_SYNC(ptep); rv = 1; + CTR1(KTR_PMAP, "pmap_fault_fix: new pte:0x%x", *ptep); } /* @@ -2453,6 +2454,8 @@ vm_paddr_t pmap_kextract(vm_offset_t va) { + if (kernel_vm_end == 0) + return (0); return (pmap_extract_locked(kernel_pmap, va)); } @@ -3302,9 +3305,11 @@ pmap_extract(pmap_t pmap, vm_offset_t va { vm_paddr_t pa; - PMAP_LOCK(pmap); + if (kernel_vm_end != 0) + PMAP_LOCK(pmap); pa = pmap_extract_locked(pmap, va); - PMAP_UNLOCK(pmap); + if (kernel_vm_end != 0) + PMAP_UNLOCK(pmap); return (pa); } @@ -3317,7 +3322,7 @@ pmap_extract_locked(pmap_t pmap, vm_offs vm_paddr_t pa; u_int l1idx; - if (pmap != kernel_pmap) + if (kernel_vm_end != 0 && pmap != kernel_pmap) PMAP_ASSERT_LOCKED(pmap); l1idx = L1_IDX(va); l1pd = pmap->pm_l1->l1_kva[l1idx]; Modified: stable/10/sys/arm/include/pmap.h ============================================================================== --- stable/10/sys/arm/include/pmap.h Wed May 14 17:01:31 2014 (r266049) +++ stable/10/sys/arm/include/pmap.h Wed May 14 17:01:35 2014 (r266050) @@ -63,7 +63,7 @@ #endif #define PTE_CACHE 6 #define PTE_DEVICE 2 -#define PTE_PAGETABLE 4 +#define PTE_PAGETABLE 6 #else #define PTE_NOCACHE 1 #define PTE_CACHE 2 @@ -491,7 +491,7 @@ extern int pmap_needs_pte_sync; #if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) #define PMAP_NEEDS_PTE_SYNC 1 #define PMAP_INCLUDE_PTE_SYNC -#elif defined(CPU_XSCALE_81342) +#elif defined(CPU_XSCALE_81342) || ARM_ARCH_6 || ARM_ARCH_7A #define PMAP_NEEDS_PTE_SYNC 1 #define PMAP_INCLUDE_PTE_SYNC #elif (ARM_MMU_SA1 == 0) @@ -561,11 +561,18 @@ extern int pmap_needs_pte_sync; #define PMAP_INCLUDE_PTE_SYNC #endif +#ifdef ARM_L2_PIPT +#define _sync_l2(pte, size) cpu_l2cache_wb_range(vtophys(pte), size) +#else +#define _sync_l2(pte, size) cpu_l2cache_wb_range(pte, size) +#endif + #define PTE_SYNC(pte) \ do { \ if (PMAP_NEEDS_PTE_SYNC) { \ cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ - cpu_l2cache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ + cpu_drain_writebuf(); \ + _sync_l2((vm_offset_t)(pte), sizeof(pt_entry_t));\ } else \ cpu_drain_writebuf(); \ } while (/*CONSTCOND*/0) @@ -575,7 +582,8 @@ do { \ if (PMAP_NEEDS_PTE_SYNC) { \ cpu_dcache_wb_range((vm_offset_t)(pte), \ (cnt) << 2); /* * sizeof(pt_entry_t) */ \ - cpu_l2cache_wb_range((vm_offset_t)(pte), \ + cpu_drain_writebuf(); \ + _sync_l2((vm_offset_t)(pte), \ (cnt) << 2); /* * sizeof(pt_entry_t) */ \ } else \ cpu_drain_writebuf(); \