From owner-cvs-ports@FreeBSD.ORG Tue May 26 11:01:39 2009 Return-Path: Delivered-To: cvs-ports@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 72E87106566C; Tue, 26 May 2009 11:01:39 +0000 (UTC) (envelope-from garga@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 621458FC17; Tue, 26 May 2009 11:01:39 +0000 (UTC) (envelope-from garga@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id n4QB1dW1052936; Tue, 26 May 2009 11:01:39 GMT (envelope-from garga@repoman.freebsd.org) Received: (from garga@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id n4QB1d3l052935; Tue, 26 May 2009 11:01:39 GMT (envelope-from garga) Message-Id: <200905261101.n4QB1d3l052935@repoman.freebsd.org> From: Renato Botelho Date: Tue, 26 May 2009 11:01:39 +0000 (UTC) To: ports-committers@FreeBSD.org, cvs-ports@FreeBSD.org, cvs-all@FreeBSD.org X-FreeBSD-CVS-Branch: HEAD Cc: Subject: cvs commit: ports/cad Makefile ports/cad/p5-Verilog-Perl Makefile distinfo pkg-descr pkg-plist X-BeenThere: cvs-ports@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: CVS commit messages for the ports tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 May 2009 11:01:39 -0000 garga 2009-05-26 11:01:39 UTC FreeBSD ports repository Modified files: cad Makefile Added files: cad/p5-Verilog-Perl Makefile distinfo pkg-descr pkg-plist Log: The Verilog-Perl library is a building point for Verilog support in the Perl language. It includes: * Verilog::Getopt which parses command line options similar to C++ and VCS. * Verilog::Language which knows the language keywords and parses numbers. * Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules. * Verilog::Parser invokes callbacks for language tokens. * Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files. * vpassert inserts PLIish warnings and assertions for any simulator. * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language. * vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes. WWW: http://www.veripool.org/wiki/verilog-perl PR: ports/134124 Submitted by: Otacílio de Araújo Ramos Neto Revision Changes Path 1.108 +1 -0 ports/cad/Makefile 1.1 +42 -0 ports/cad/p5-Verilog-Perl/Makefile (new) 1.1 +3 -0 ports/cad/p5-Verilog-Perl/distinfo (new) 1.1 +19 -0 ports/cad/p5-Verilog-Perl/pkg-descr (new) 1.1 +33 -0 ports/cad/p5-Verilog-Perl/pkg-plist (new)