From owner-freebsd-hardware@FreeBSD.ORG Mon Dec 29 11:06:35 2003 Return-Path: Delivered-To: freebsd-hardware@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 3498416A4CE for ; Mon, 29 Dec 2003 11:06:35 -0800 (PST) Received: from smtp3.sentex.ca (smtp3.sentex.ca [64.7.153.18]) by mx1.FreeBSD.org (Postfix) with ESMTP id C1EA943D1F for ; Mon, 29 Dec 2003 11:03:22 -0800 (PST) (envelope-from damian@sentex.net) Received: from lava.sentex.ca (pyroxene.sentex.ca [199.212.134.18]) by smtp3.sentex.ca (8.12.10/8.12.10) with ESMTP id hBTJ1qHF043817; Mon, 29 Dec 2003 14:01:52 -0500 (EST) (envelope-from damian@sentex.net) Received: from pegmatite.sentex.ca (pegmatite.sentex.ca [192.168.42.92]) by lava.sentex.ca (8.12.9p2/8.12.9) with ESMTP id hBTJ1tXv033763; Mon, 29 Dec 2003 14:01:55 -0500 (EST) (envelope-from damian@sentex.net) Received: by pegmatite.sentex.ca (Postfix, from userid 1001) id 07209171CE; Mon, 29 Dec 2003 14:01:46 -0500 (EST) Date: Mon, 29 Dec 2003 14:01:46 -0500 From: Damian Gerow To: admin@forkthepenguin.com Message-ID: <20031229190146.GR883@sentex.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-GPG-Key-Id: 0xB841F142 X-GPG-Fingerprint: C7C1 E1D1 EC06 7C86 AF7C 57E6 173D 9CF6 B841 F142 X-Habeas-SWE-1: winter into spring X-Habeas-SWE-2: brightly anticipated X-Habeas-SWE-3: like Habeas SWE (tm) X-Habeas-SWE-4: Copyright 2002 Habeas (tm) X-Habeas-SWE-5: Sender Warranted Email (SWE) (tm). The sender of this X-Habeas-SWE-6: email in exchange for a license for this Habeas X-Habeas-SWE-7: warrant mark warrants that this is a Habeas Compliant X-Habeas-SWE-8: Message (HCM) and not spam. Please report use of this X-Habeas-SWE-9: mark in spam to . User-Agent: Mutt/1.5.4i X-Virus-Scanned: by amavisd-new cc: freebsd-hardware@freebsd.org Subject: Re: Kernel Optimizations for Processors X-BeenThere: freebsd-hardware@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: General discussion of FreeBSD hardware List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 29 Dec 2003 19:06:35 -0000 Thus spake admin@forkthepenguin.com (admin@forkthepenguin.com) [28/12/03 00:16]: > Is there a method for determining what options can be incorporated for a > specific processor? The unit in question is a VIA C3 Samuel2 processor > running at 800 Mhz. I've found many clues that this uses Cyrix > instructions although the chipset uses the Centaur core. This is supposed > to be an i686, but I've seen some issues on a Linux system with the same > processor that required the kernel to be built with i586. There's been a number of discussions about this over the past few months. Take a quick peak through the archives. In short: the GCC folk (at least for 2.95.x) assume that a 686-compatible chip understands CMOV. *Some* of the C3 cores understand it, others do not. I was under the impression that the Samuel2 /did/ understand it. Understanding CMOV is not a requirement for 686. I know for a fact that the Ezra and Ezra-T chips (what I'm using) do *not* understand CMOV. I think you get ever-so-slightly better performance if you set your ARCH to k6-2, though I use mine as i586/mmx. As for the kernel configuration, I left mine at I686_CPU, as the C3 /is/ a 686-class CPU. I think the history of the C3 is that VIA bought out Cyrix and Centaur, and brought both of them together. Technically, the chip is Cyrix at its core, I *believe*. Correct me if I'm wrong. The newer chips (Nehemiah and on) are probably different. > # CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1). This is a 686-class CPU, not a 586-class CPU. > # CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct > # mapped mode. Default is 2-way set associative mode. Again -- 486 vs. 686. > # CPU_CYRIX_NO_LOCK enables weak locking for the entire address space > # of Cyrix 6x86 and 6x86MX CPUs by setting the NO_LOCK bit of CCR1. > # Otherwise, the NO_LOCK bit of CCR1 is cleared. (NOTE 3) Never used it. > # CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables > # reorder). This option should not be used if you use memory mapped > # I/O device(s). Never used it. > # CPU_IORT defines I/O clock delay time (NOTE 1). Default values of > # I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively > # (no clock delay). Never used it. > # CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1). 586 vs. 686. > # CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD > # K5/K6/K6-2 cpus. Used it, never bothered to see if it made a difference. > # CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache > # flush at hold state. Never used it -- 486 vs. 686. > # CYRIX_CACHE_REALLY_WORKS enables (1) CPU cache on Cyrix 486 CPUs > # without cache flush at hold state, and (2) write-back CPU cache on > # Cyrix 6x86 whose revision < 2.7 (NOTE 2). Used it, never bothered to see if it made a difference. > # NO_F00F_HACK disables the hack that prevents Pentiums (and ONLY > # Pentiums) from locking up when a LOCK CMPXCHG8B instruction is > # executed. This option is only needed if I586_CPU is also defined, > # and should be included for any non-Pentium CPU that defines it. 'and ONLY Pentiums' > Copyright (c) 1992-2003 The FreeBSD Project. > Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 > The Regents of the University of California. All rights reserved. > FreeBSD 4.9-RELEASE #0: Mon Oct 27 17:51:09 GMT 2003 > root@freebsd-stable.sentex.ca:/usr/obj/usr/src/sys/GENERIC > Timecounter "i8254" frequency 1193182 Hz > CPU: VIA C3 Samuel 2 (801.82-MHz 686-class CPU) > Origin = "CentaurHauls" Id = 0x673 Stepping = 3 > Features=0x803035 Well, I guess the Samuel2 doesn't understand CMOV either. Maybe it was the Samuel that did...? Dunno. The Nehemiah does, though.