From owner-svn-src-all@FreeBSD.ORG Sun Feb 23 22:52:48 2014 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id E205C359; Sun, 23 Feb 2014 22:52:48 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id CE0B81E18; Sun, 23 Feb 2014 22:52:48 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s1NMqm21075702; Sun, 23 Feb 2014 22:52:48 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s1NMqmI5075701; Sun, 23 Feb 2014 22:52:48 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201402232252.s1NMqmI5075701@svn.freebsd.org> From: Ian Lepore Date: Sun, 23 Feb 2014 22:52:48 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r262411 - head/sys/arm/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 23 Feb 2014 22:52:49 -0000 Author: ian Date: Sun Feb 23 22:52:48 2014 New Revision: 262411 URL: http://svnweb.freebsd.org/changeset/base/262411 Log: If the L2 cache type is PIPT, pass a physical address for a flush. While this is technically more correct, I don't think it much matters, because the only thing in the tree that calls cpu_flush_dcache() is md(4) and I'm > 99% sure it's bogus that it does so; md has no ability to do anything that can perturb data cache coherency. Modified: head/sys/arm/arm/machdep.c Modified: head/sys/arm/arm/machdep.c ============================================================================== --- head/sys/arm/arm/machdep.c Sun Feb 23 22:50:22 2014 (r262410) +++ head/sys/arm/arm/machdep.c Sun Feb 23 22:52:48 2014 (r262411) @@ -410,7 +410,11 @@ cpu_flush_dcache(void *ptr, size_t len) { cpu_dcache_wb_range((uintptr_t)ptr, len); +#ifdef ARM_L2_PIPT + cpu_l2cache_wb_range((uintptr_t)vtophys(ptr), len); +#else cpu_l2cache_wb_range((uintptr_t)ptr, len); +#endif } /* Get current clock frequency for the given cpu id. */