From owner-p4-projects@FreeBSD.ORG Thu Apr 8 13:55:02 2010 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 1731B106568D; Thu, 8 Apr 2010 13:55:02 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id B5827106567B; Thu, 8 Apr 2010 13:55:01 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from cyrus.watson.org (cyrus.watson.org [65.122.17.42]) by mx1.freebsd.org (Postfix) with ESMTP id 23C918FC2F; Thu, 8 Apr 2010 13:55:01 +0000 (UTC) Received: from bigwig.baldwin.cx (66.111.2.69.static.nyinternet.net [66.111.2.69]) by cyrus.watson.org (Postfix) with ESMTPSA id AF60346B53; Thu, 8 Apr 2010 09:55:00 -0400 (EDT) Received: from jhbbsd.localnet (smtp.hudson-trading.com [209.249.190.9]) by bigwig.baldwin.cx (Postfix) with ESMTPA id C907D8A01F; Thu, 8 Apr 2010 09:54:59 -0400 (EDT) From: John Baldwin To: Rafal Jaworowski Date: Thu, 8 Apr 2010 08:57:53 -0400 User-Agent: KMail/1.12.1 (FreeBSD/7.3-CBSD-20100217; KDE/4.3.1; amd64; ; ) References: <201004071502.o37F2Rou064473@repoman.freebsd.org> In-Reply-To: <201004071502.o37F2Rou064473@repoman.freebsd.org> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-15" Content-Transfer-Encoding: 7bit Message-Id: <201004080857.53917.jhb@freebsd.org> X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.0.1 (bigwig.baldwin.cx); Thu, 08 Apr 2010 09:54:59 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.95.1 at bigwig.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-1.8 required=4.2 tests=AWL,BAYES_00 autolearn=ham version=3.2.5 X-Spam-Checker-Version: SpamAssassin 3.2.5 (2008-06-10) on bigwig.baldwin.cx Cc: Perforce Change Reviews Subject: Re: PERFORCE change 176621 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Apr 2010 13:55:02 -0000 On Wednesday 07 April 2010 11:02:27 am Rafal Jaworowski wrote: > http://p4web.freebsd.org/@@176621?ac=10 > > Change 176621 by raj@raj_fdt on 2010/04/07 15:02:20 > > Provide PCI-E defines. > > Affected files ... > > .. //depot/projects/fdt/sys/dev/pci/pcireg.h#3 edit > > Differences ... > > ==== //depot/projects/fdt/sys/dev/pci/pcireg.h#3 (text+ko) ==== > > @@ -218,6 +218,17 @@ > > #define PCIR_PCCARDIF_2 0x44 > > + > +/* PCIE registers */ > +#define PCIR_DCR 0x54 > +#define PCIM_DCR_URR 0x0008 > +#define PCIM_DCR_FER 0x0004 > +#define PCIM_DCR_NFER 0x0002 > +#define PCIR_DSR 0x56 > +#define PCIR_LTSSM 0x404 > +#define PCIM_LTSSM_L0 0x16 Err, are you sure about these? Generally the PCI-e registers are part of the PCI-e capability and are not a fixed offset. Also, we already have constants for various PCI-e registers in pcireg.h like so: /* PCI Express definitions */ #define PCIR_EXPRESS_FLAGS 0x2 #define PCIM_EXP_FLAGS_VERSION 0x000F #define PCIM_EXP_FLAGS_TYPE 0x00F0 #define PCIM_EXP_TYPE_ENDPOINT 0x0000 #define PCIM_EXP_TYPE_LEGACY_ENDPOINT 0x0010 #define PCIM_EXP_TYPE_ROOT_PORT 0x0040 #define PCIM_EXP_TYPE_UPSTREAM_PORT 0x0050 #define PCIM_EXP_TYPE_DOWNSTREAM_PORT 0x0060 #define PCIM_EXP_TYPE_PCI_BRIDGE 0x0070 #define PCIM_EXP_TYPE_PCIE_BRIDGE 0x0080 #define PCIM_EXP_TYPE_ROOT_INT_EP 0x0090 #define PCIM_EXP_TYPE_ROOT_EC 0x00a0 #define PCIM_EXP_FLAGS_SLOT 0x0100 #define PCIM_EXP_FLAGS_IRQ 0x3e00 #define PCIR_EXPRESS_DEVICE_CAP 0x4 #define PCIM_EXP_CAP_MAX_PAYLOAD 0x0007 #define PCIR_EXPRESS_DEVICE_CTL 0x8 #define PCIM_EXP_CTL_RELAXED_ORD_ENABLE 0x0010 #define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0 #define PCIM_EXP_CTL_NOSNOOP_ENABLE 0x0800 #define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000 #define PCIR_EXPRESS_DEVICE_STA 0xa #define PCIM_EXP_STA_CORRECTABLE_ERROR 0x0001 #define PCIM_EXP_STA_NON_FATAL_ERROR 0x0002 #define PCIM_EXP_STA_FATAL_ERROR 0x0004 #define PCIM_EXP_STA_UNSUPPORTED_REQ 0x0008 #define PCIM_EXP_STA_AUX_POWER 0x0010 #define PCIM_EXP_STA_TRANSACTION_PND 0x0020 #define PCIR_EXPRESS_LINK_CAP 0xc #define PCIM_LINK_CAP_MAX_SPEED 0x0000000f #define PCIM_LINK_CAP_MAX_WIDTH 0x000003f0 #define PCIM_LINK_CAP_ASPM 0x00000c00 #define PCIM_LINK_CAP_L0S_EXIT 0x00007000 #define PCIM_LINK_CAP_L1_EXIT 0x00038000 #define PCIM_LINK_CAP_PORT 0xff000000 #define PCIR_EXPRESS_LINK_CTL 0x10 #define PCIR_EXPRESS_LINK_STA 0x12 #define PCIM_LINK_STA_SPEED 0x000f #define PCIM_LINK_STA_WIDTH 0x03f0 #define PCIM_LINK_STA_TRAINING_ERROR 0x0400 #define PCIM_LINK_STA_TRAINING 0x0800 #define PCIM_LINK_STA_SLOT_CLOCK 0x1000 #define PCIR_EXPRESS_SLOT_CAP 0x14 #define PCIR_EXPRESS_SLOT_CTL 0x18 #define PCIR_EXPRESS_SLOT_STA 0x1a #define PCIR_EXPRESS_ROOT_CTL 0x1c #define PCIR_EXPRESS_ROOT_STA 0x20 > + > + > /* PCI device class, subclass and programming interface definitions */ > > #define PCIC_OLD 0x00 > -- John Baldwin