From owner-p4-projects@FreeBSD.ORG Thu Nov 30 01:37:14 2006 Return-Path: X-Original-To: p4-projects@freebsd.org Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id BEE7C16A40F; Thu, 30 Nov 2006 01:37:14 +0000 (UTC) X-Original-To: perforce@freebsd.org Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 92D6616A407 for ; Thu, 30 Nov 2006 01:37:14 +0000 (UTC) (envelope-from imp@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [69.147.83.41]) by mx1.FreeBSD.org (Postfix) with ESMTP id 7905143C9D for ; Thu, 30 Nov 2006 01:37:09 +0000 (GMT) (envelope-from imp@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.13.6/8.13.6) with ESMTP id kAU1bE2m090596 for ; Thu, 30 Nov 2006 01:37:14 GMT (envelope-from imp@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.13.6/8.13.4/Submit) id kAU1bErj090593 for perforce@freebsd.org; Thu, 30 Nov 2006 01:37:14 GMT (envelope-from imp@freebsd.org) Date: Thu, 30 Nov 2006 01:37:14 GMT Message-Id: <200611300137.kAU1bErj090593@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to imp@freebsd.org using -f From: Warner Losh To: Perforce Change Reviews Cc: Subject: PERFORCE change 110700 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Nov 2006 01:37:15 -0000 http://perforce.freebsd.org/chv.cgi?CH=110700 Change 110700 by imp@imp_lighthouse on 2006/11/30 01:36:39 Interrupt driven doesn't work, but polling does. Go figure. Affected files ... .. //depot/projects/arm/src/sys/arm/at91/at91_spi.c#13 edit .. //depot/projects/arm/src/sys/arm/at91/at91_spireg.h#7 edit Differences ... ==== //depot/projects/arm/src/sys/arm/at91/at91_spi.c#13 (text+ko) ==== @@ -98,8 +98,8 @@ * Allocate DMA tags and maps */ err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, - BUS_SPACE_MAXADDR, NULL, NULL, 2058, 1, 2048, BUS_DMA_ALLOCNOW, - NULL, NULL, &sc->dmatag); + BUS_SPACE_MAXADDR, NULL, NULL, 1024 * 10, 1, 1024 * 10, + BUS_DMA_ALLOCNOW, NULL, NULL, &sc->dmatag); if (err != 0) goto out; for (i = 0; i < 4; i++) { @@ -231,25 +231,32 @@ cmd->tx_cmd_sz, at91_getaddr, &addr, 0) != 0) goto out; WR4(sc, PDC_RPR, addr); - WR4(sc, PDC_RCR, cmd->tx_cmd_sz); + WR4(sc, PDC_RCR, cmd->rx_cmd_sz); bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD); mode[i++] = BUS_DMASYNC_POSTREAD; if (cmd->rx_data_sz > 0) { if (bus_dmamap_load(sc->dmatag, sc->map[i], cmd->rx_data, - cmd->tx_data_sz, at91_getaddr, &addr, 0) != 0) + cmd->rx_data_sz, at91_getaddr, &addr, 0) != 0) goto out; WR4(sc, PDC_RNPR, addr); WR4(sc, PDC_RNCR, cmd->rx_data_sz); bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD); mode[i++] = BUS_DMASYNC_POSTREAD; } - WR4(sc, SPI_IER, SPI_SR_ENDRX); + rxdone = sc->rxdone; +#if 0 + WR4(sc, SPI_IER, SPI_SR_RXBUFF); WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN | PDC_PTCR_RXTEN); - rxdone = sc->rxdone; do { err = msleep(&sc->rxdone, NULL, PCATCH | PZERO, "spi", hz); } while (rxdone == sc->rxdone && err != EINTR); +#else + WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN | PDC_PTCR_RXTEN); + while (!(RD4(sc, SPI_SR) & SPI_SR_RXBUFF)) + continue; + err = 0; +#endif WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); if (err == 0) { for (j = 0; j < i; j++) @@ -271,14 +278,14 @@ uint32_t sr; sr = RD4(sc, SPI_SR) & RD4(sc, SPI_IMR); - if (sr & SPI_SR_ENDRX) { + if (sr & SPI_SR_RXBUFF) { sc->rxdone++; - WR4(sc, SPI_IDR, SPI_SR_ENDRX); + WR4(sc, SPI_IDR, SPI_SR_RXBUFF); wakeup(&sc->rxdone); } - if (sr & ~SPI_SR_ENDRX) { + if (sr & ~SPI_SR_RXBUFF) { device_printf(sc->dev, "Unexpected ISR %#x\n", sr); - WR4(sc, SPI_IDR, sr & ~SPI_SR_ENDRX); + WR4(sc, SPI_IDR, sr & ~SPI_SR_RXBUFF); } } ==== //depot/projects/arm/src/sys/arm/at91/at91_spireg.h#7 (text+ko) ==== @@ -51,7 +51,7 @@ #define SPI_SR_OVRES 0x00008 #define SPI_SR_ENDRX 0x00010 #define SPI_SR_ENDTX 0x00020 -#define SPI_SR_RXBUFE 0x00040 +#define SPI_SR_RXBUFF 0x00040 #define SPI_SR_TXBUFE 0x00080 #define SPI_SR_SPIENS 0x10000 #define SPI_IER 0x14 /* IER: Interrupt Enable Regsiter */