From owner-svn-src-user@FreeBSD.ORG Wed Apr 21 22:18:27 2010 Return-Path: Delivered-To: svn-src-user@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 82134106564A; Wed, 21 Apr 2010 22:18:27 +0000 (UTC) (envelope-from jmallett@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 58A208FC19; Wed, 21 Apr 2010 22:18:27 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o3LMIR90084607; Wed, 21 Apr 2010 22:18:27 GMT (envelope-from jmallett@svn.freebsd.org) Received: (from jmallett@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o3LMIRau084604; Wed, 21 Apr 2010 22:18:27 GMT (envelope-from jmallett@svn.freebsd.org) Message-Id: <201004212218.o3LMIRau084604@svn.freebsd.org> From: Juli Mallett Date: Wed, 21 Apr 2010 22:18:27 +0000 (UTC) To: src-committers@freebsd.org, svn-src-user@freebsd.org X-SVN-Group: user MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r207024 - user/jmallett/octeon/contrib/gcc/config/mips X-BeenThere: svn-src-user@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the experimental " user" src tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Apr 2010 22:18:27 -0000 Author: jmallett Date: Wed Apr 21 22:18:27 2010 New Revision: 207024 URL: http://svn.freebsd.org/changeset/base/207024 Log: Add "octeon" processor as a MIPS64R2 variant. Modified: user/jmallett/octeon/contrib/gcc/config/mips/mips.c user/jmallett/octeon/contrib/gcc/config/mips/mips.h Modified: user/jmallett/octeon/contrib/gcc/config/mips/mips.c ============================================================================== --- user/jmallett/octeon/contrib/gcc/config/mips/mips.c Wed Apr 21 22:17:25 2010 (r207023) +++ user/jmallett/octeon/contrib/gcc/config/mips/mips.c Wed Apr 21 22:18:27 2010 (r207024) @@ -763,6 +763,9 @@ const struct mips_cpu_info mips_cpu_info { "sb1a", PROCESSOR_SB1A, 64 }, { "sr71000", PROCESSOR_SR71000, 64 }, + /* MIPS64R2 */ + { "octeon", PROCESSOR_OCTEON, 65 }, + /* End marker */ { 0, 0, 0 } }; @@ -9944,6 +9947,7 @@ mips_issue_rate (void) case PROCESSOR_R5500: case PROCESSOR_R7000: case PROCESSOR_R9000: + case PROCESSOR_OCTEON: return 2; case PROCESSOR_SB1: Modified: user/jmallett/octeon/contrib/gcc/config/mips/mips.h ============================================================================== --- user/jmallett/octeon/contrib/gcc/config/mips/mips.h Wed Apr 21 22:17:25 2010 (r207023) +++ user/jmallett/octeon/contrib/gcc/config/mips/mips.h Wed Apr 21 22:18:27 2010 (r207024) @@ -41,6 +41,7 @@ enum processor_type { PROCESSOR_24K, PROCESSOR_24KX, PROCESSOR_M4K, + PROCESSOR_OCTEON, PROCESSOR_R3900, PROCESSOR_R6000, PROCESSOR_R4000, @@ -213,6 +214,7 @@ extern const struct mips_rtx_cost_data * #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \ || mips_arch == PROCESSOR_SB1A) #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) +#define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON) /* Scheduling target defines. */ #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) @@ -228,6 +230,7 @@ extern const struct mips_rtx_cost_data * #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ || mips_tune == PROCESSOR_SB1A) +#define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON) /* True if the pre-reload scheduler should try to create chains of multiply-add or multiply-subtract instructions. For example,