From owner-freebsd-arch@FreeBSD.ORG Thu Jun 18 05:32:02 2009 Return-Path: Delivered-To: arch@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 9D629106566B; Thu, 18 Jun 2009 05:32:02 +0000 (UTC) (envelope-from jroberson@jroberson.net) Received: from mail-px0-f203.google.com (mail-px0-f203.google.com [209.85.216.203]) by mx1.freebsd.org (Postfix) with ESMTP id 6CB028FC13; Thu, 18 Jun 2009 05:32:02 +0000 (UTC) (envelope-from jroberson@jroberson.net) Received: by mail-px0-f203.google.com with SMTP id 41so279098pxi.3 for ; Wed, 17 Jun 2009 22:32:02 -0700 (PDT) Received: by 10.114.76.10 with SMTP id y10mr1499881waa.83.1245303122036; Wed, 17 Jun 2009 22:32:02 -0700 (PDT) Received: from ?10.0.1.198? (udp016664uds.hawaiiantel.net [72.235.41.117]) by mx.google.com with ESMTPS id l38sm2673854waf.26.2009.06.17.22.31.59 (version=SSLv3 cipher=RC4-MD5); Wed, 17 Jun 2009 22:32:00 -0700 (PDT) Date: Wed, 17 Jun 2009 19:31:58 -1000 (HST) From: Jeff Roberson X-X-Sender: jroberson@desktop To: Julian Elischer In-Reply-To: <4A39C3CD.8020909@elischer.org> Message-ID: References: <20090609201127.GA50903@alchemy.franken.de> <4A2F1148.9090706@freebsd.org> <20090617.210318.1878034641.imp@bsdimp.com> <4A39C3CD.8020909@elischer.org> User-Agent: Alpine 2.00 (BSF 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Cc: arch@FreeBSD.org, grehan@FreeBSD.org, marius@alchemy.franken.de Subject: Re: Dynamic pcpu, arm, mips, powerpc, sun, etc. help needed X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 18 Jun 2009 05:32:03 -0000 On Wed, 17 Jun 2009, Julian Elischer wrote: > Jeff Roberson wrote: >> On Wed, 17 Jun 2009, M. Warner Losh wrote: >> >>> In message: >>> Jeff Roberson writes: >>> : >>> : On Tue, 9 Jun 2009, Peter Grehan wrote: >>> : >>> : >> As for sparc64 allocating the storage for the dynamic area >>> : >> from end probably isn't a good idea as the pmap code assumes >>> : >> that the range from KERNBASE to end is covered by the pages >>> : >> allocated by and locked into the TLB for the kernel by the >>> : >> loader >>> : > >>> : > Ditto for ppc. It's possible to get the additional space from within >>> or >>> : > after return from pmap_bootstrap() (like thread0's kstack, or the >>> msgbuf). >>> : >>> : http://people.freebsd.org/~jeff/dpcpu.diff >>> : >>> : I have updated this patch based on feedback relating to various >>> : architectures md code. I tried to model most architectures after the >>> way >>> : msgbuf memory was taken. I have no capacity to test anything other than >>> : i386 and amd64. ARM is reported to work with one minor diff. >>> Apparently >>> : sparc64 worked with the earlier diff but this should be cleaner. If >>> : anyone can report back on sparc64, mips, or powerpc, I'd appreciate it. >>> >>> >>> I don't understand this part of the patch: >>> >>> Index: mips/mips/mp_machdep.c >>> =================================================================== >>> --- mips/mips/mp_machdep.c (revision 194275) >>> +++ mips/mips/mp_machdep.c (working copy) >>> @@ -224,12 +224,15 @@ static int >>> smp_start_secondary(int cpuid) >>> { >>> struct pcpu *pcpu; >>> + void *dpcpu; >>> int i; >>> >>> if (bootverbose) >>> printf("smp_start_secondary: starting cpu %d\n", cpuid); >>> >>> + dpcpu = (void *)kmem_alloc(kernel_map, DPCPU_SIZE); >>> pcpu_init(&__pcpu[cpuid], cpuid, sizeof(struct pcpu)); >>> + dpcpu_init(dpcpu, cpuid); >>> >>> if (bootverbose) >>> printf("smp_start_secondary: cpu %d started\n", cpuid); >>> >>> So were adding a dynamic per-cpu area, in addition to the fixed part? >> >> Yes, the fixed part is for legacy and very frequently accessed items that >> need fixed addresses. The dynamic area is for convenience and is slightly >> more expensive to access. It also has addresses that are not resolved >> until link time. >> >> The fixed area uses a static structure with a size that is known at compile >> time. The dynamic part is only known at link time and so must be allocated >> seperately. > > > the compilers know of TLS and it wouldn't take much in the backend > code to make the 'thread' keyworkd for TLS generate per-cpu data > instead of per-thread data.. basically the register settings for TLS > would have to be replaced by per cpu registers but .. wait we do > that.. > since the per-thread registers in the kernel point to per-cpu data > and are kept correct by the scheduler, shouldn't the TLS code "just > work" if we put the correct data structures in the right places? We discussed that at bsdcan and apparently it's not that simple. dfr seemed to think it would take quite some time to do the kernel linker support. There also may be issues because the compiler is free to cache thread local data but not per-cpu data so there may be a mismatch there. It would be nice ultimately to make this work but at that time DPCPU_ could just become a wrapper around __thread. Thanks, Jeff > >> >> Jeff >> >>> >>> Warner >>> >> _______________________________________________ >> freebsd-arch@freebsd.org mailing list >> http://lists.freebsd.org/mailman/listinfo/freebsd-arch >> To unsubscribe, send any mail to "freebsd-arch-unsubscribe@freebsd.org" >