From owner-freebsd-hackers Wed Dec 17 17:22:52 1997 Return-Path: Received: (from root@localhost) by hub.freebsd.org (8.8.7/8.8.7) id RAA03687 for hackers-outgoing; Wed, 17 Dec 1997 17:22:52 -0800 (PST) (envelope-from owner-freebsd-hackers) Received: from arg1.demon.co.uk (arg1.demon.co.uk [194.222.34.166]) by hub.freebsd.org (8.8.7/8.8.7) with ESMTP id RAA03353 for ; Wed, 17 Dec 1997 17:17:16 -0800 (PST) (envelope-from arg@arg1.demon.co.uk) Received: (from arg@localhost) by arg1.demon.co.uk (8.8.5/8.8.5) id BAA17849; Thu, 18 Dec 1997 01:15:51 GMT Date: Thu, 18 Dec 1997 01:15:50 +0000 (GMT) From: Andrew Gordon X-Sender: arg@server.arg.sj.co.uk To: Mike Smith cc: FreeBSD Hackers Subject: Re: 3com 3c509 card In-Reply-To: <199712170334.OAA01300@word.smith.net.au> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: owner-freebsd-hackers@freebsd.org X-Loop: FreeBSD.org Precedence: bulk On Wed, 17 Dec 1997, Mike Smith wrote: > > If I can't route 4 ethernet interfaces with SMC Ultras then a rigorous > > academic exercise has no value for my purposes. I just want a rough > > projection that's reasonably accurate. > > "AT Bus Design" (Edward Solari, Annabooks), p 6-101, quoted without > permission, excerpt from table 6-3: ISA AND E-ISA PLATFORM STANDARD > ACCESS MEMORY CYCLE LENGTH Note that a _standard_ cycle isn't the fastest possible cycle: 16-bit memory cycles have one wait state, but a board can generate 0 w/s cycles by holding NOWS* low. Since this is only applicable to memory cycles, this is the reason the WD/SMC boards (memory mapped) used to be considered superior to NE2000 clones (I/O cycles, hence 1 w/s min). > > BUS OWNER CYCLE BEGINS CYCLE ENDS CYCLE CYCLE > SIZE LENGTH > --------------------------------------------------------------- > PLAT FORM (sic) .5 TCLK TO END COMMAND 8 BITS 6 TCLK > CPU ACT BALE ACT PERIOD 16 BITS 3 TCLK > > For reference, TCLK is the period of BCLK, ie. 1 TCLK ~= 120ns for the > standard 8.33MHz BCLK. > So a 16-bit memory cycle on the ISA bus takes at least 360ns. > If you flip that the other way around and account for the other .5 TCLK > idle before BALE can go active again, ??? You appear to be double-counting here - that 0.5 cycle before BALE is included in the 3 cycles (or 2 cycles at 0 w/s). After all, since the polarity of BCLK doesn't change, the interval between successive accesses (assuming no other activity on the ISA bus) _must_ be an integer number of cycles, so the answer can't possibly be 2.5. > you get about 2.5 16-bit cycles > per microsecond, or about 5MB/sec ISA memory bandwidth. If you can actually generate back-to-back 16-bit 0 w/s memory cycles, you get 8Mbyte/sec. Ability to do so presumably depends substantially on the behaviour of the ISA bridge behaviour in the chipset on modern machines; the relationship of the ISA bus to CPU cycles is non-obvious.