From owner-svn-src-all@FreeBSD.ORG Tue Feb 25 15:22:41 2014 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 5C2E917F; Tue, 25 Feb 2014 15:22:41 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 2D9AB15B4; Tue, 25 Feb 2014 15:22:41 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s1PFMfJ5071386; Tue, 25 Feb 2014 15:22:41 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s1PFMfHr071385; Tue, 25 Feb 2014 15:22:41 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201402251522.s1PFMfHr071385@svn.freebsd.org> From: Ian Lepore Date: Tue, 25 Feb 2014 15:22:41 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r262482 - head/sys/arm/freescale/imx X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Feb 2014 15:22:41 -0000 Author: ian Date: Tue Feb 25 15:22:40 2014 New Revision: 262482 URL: http://svnweb.freebsd.org/changeset/base/262482 Log: Invalidate the SCU cache tag ram on all 4 cores, not just 1-3. I misread Juergen's original code, it was doing all 4 cores. Also remove the L2 cache invalidate operation, this code runs before L2 is activated. Modified: head/sys/arm/freescale/imx/imx6_mp.c Modified: head/sys/arm/freescale/imx/imx6_mp.c ============================================================================== --- head/sys/arm/freescale/imx/imx6_mp.c Tue Feb 25 14:47:34 2014 (r262481) +++ head/sys/arm/freescale/imx/imx6_mp.c Tue Feb 25 15:22:40 2014 (r262482) @@ -113,11 +113,11 @@ platform_mp_start_ap(void) panic("Couldn't map the system reset controller (SRC)\n"); /* - * Invalidate SCU cache tags. The 0x0000fff0 constant invalidates all - * ways on all cores 1-3 (leaving core 0 alone). Per the ARM docs, it's - * harmless to write to the bits for cores that are not present. + * Invalidate SCU cache tags. The 0x0000ffff constant invalidates all + * ways on all cores 0-3. Per the ARM docs, it's harmless to write to + * the bits for cores that are not present. */ - bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000fff0); + bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff); /* * Erratum ARM/MP: 764369 (problems with cache maintenance). @@ -128,13 +128,17 @@ platform_mp_start_ap(void) bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, val | SCU_DIAG_DISABLE_MIGBIT); - /* Enable the SCU. */ + /* + * Enable the SCU, then clean the cache on this core. After these two + * operations the cache tag ram in the SCU is coherent with the contents + * of the cache on this core. The other cores aren't running yet so + * their caches can't contain valid data yet, but we've initialized + * their SCU tag ram above, so they will be coherent from startup. + */ val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG); bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, val | SCU_CONTROL_ENABLE); - cpu_idcache_wbinv_all(); - cpu_l2cache_wbinv_all(); /* * For each AP core, set the entry point address and argument registers,