From owner-freebsd-drivers@freebsd.org Sun Aug 19 10:11:31 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 275FD10889E3; Sun, 19 Aug 2018 10:11:31 +0000 (UTC) (envelope-from danny@cs.huji.ac.il) Received: from kabab.cs.huji.ac.il (kabab.cs.huji.ac.il [132.65.116.210]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id A0CB98FB4B; Sun, 19 Aug 2018 10:11:30 +0000 (UTC) (envelope-from danny@cs.huji.ac.il) Received: from bach.cs.huji.ac.il ([132.65.80.20]) by kabab.cs.huji.ac.il with esmtp id 1frKg0-000E7j-0O; Sun, 19 Aug 2018 13:11:16 +0300 From: Daniel Braniss Message-Id: <3C2D99A1-DC1C-4915-81DE-7F9D48AAB10E@cs.huji.ac.il> Mime-Version: 1.0 (Mac OS X Mail 11.5 \(3445.9.1\)) Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD Date: Sun, 19 Aug 2018 13:11:15 +0300 In-Reply-To: <1534523216.27158.17.camel@freebsd.org> Cc: Rajesh Kumar , freebsd-drivers@freebsd.org, freebsd-hackers@freebsd.org To: Ian Lepore References: <1534523216.27158.17.camel@freebsd.org> X-Mailer: Apple Mail (2.3445.9.1) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.27 X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 19 Aug 2018 10:11:31 -0000 > On 17 Aug 2018, at 19:26, Ian Lepore wrote: >=20 > On Fri, 2018-08-17 at 11:48 +0530, Rajesh Kumar wrote: >> Hi, >>=20 >> I am trying to use the I2C designware controller driver available in >> FreeBSD (ig4_iic.c) in our boards. >>=20 >> Is there a clean way, I can set the I2C bus frequency from the = controller >> driver itself, rather than using device hints, FDT, tunables etc., >> Something like, if the driver is loaded for our boards (identified = using >> the PCI or ACPI ID's), then the frequency of the I2C bus needs to be >> hardcoded from driver itself. This is to avoid additional configs = from the >> config file. >>=20 >> I tried adding a new interface "iicbus_set_frequency" (in line with >> iicbus_get_frequency) and tried calling that from the ig4 driver = after the >> "iicbus" child is added. But, iicbus instance is created only after = ig4 >> driver is loaded. So, calling iicbus_set_frequency after child = addition >> leads to system panic (as there is no iicbus softc at this point). >>=20 >> Let me know if you need any details. >>=20 >> Thanks, >> Rajesh. >=20 > I don't really understand what you're asking for. The ig4_iic > controller driver doesn't appear to support bus frequency settings at > all, it just loads hard-coded values into the clock high/low registers > and never changes them. If you want to locally modify the driver to = run > at a different hard-coded speed for your application, just change = lines > 589-592 in ig4_iic.c and continue to ignore the speed set by the bus > driver when handling iicbus_reset. >=20 on the arm/allwinner it=E2=80=99s set at 100Khz, and though there are = sysctls to change it, it=E2=80=99s ignored :-) I could change this, but is there some hidden reason that it=E2=80=99s = so? danny From owner-freebsd-drivers@freebsd.org Sun Aug 19 10:29:17 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id F25671089205; Sun, 19 Aug 2018 10:29:16 +0000 (UTC) (envelope-from manu@bidouilliste.com) Received: from mail.blih.net (mail.blih.net [212.83.177.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mail.blih.net", Issuer "mail.blih.net" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4C58F7070C; Sun, 19 Aug 2018 10:29:16 +0000 (UTC) (envelope-from manu@bidouilliste.com) Received: from mail.blih.net (mail.blih.net [212.83.177.182]) by mail.blih.net (OpenSMTPD) with ESMTP id 7f6d23e6; Sun, 19 Aug 2018 12:29:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=bidouilliste.com; h=date :from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=mail; bh=lGPm6ALSUJ/y6rVjVG1K2NpNQCY=; b=OFMOgvlMWD5qvQDAAaL1I8qHXfFs nLM0aE3HDlLVeuqZTY8IHtYgDdIr+9GGqBWpPnpGd071Mm2SuSTF/VB6UGSnYRyA a7kd8BW5kqeEqmtmo1Y7H2GyMaWVd4AyL6h3pK4gydVg9hAN2tJXj8Z52X83XVu7 cs83qoxoZLoGQIc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=bidouilliste.com; h=date :from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; q=dns; s= mail; b=OeYq0SnFXpeiKxelesQn2NMeJ/ru1d3fpdlMqqNDXCuzTyycY6dgVCvz k8nI7agCkFwjxDM8vp9PaOxQo5aXcdI6Bl6wpaewUCKulAmFS0zzhD/wzteqZV0S qoK5uc5Z7WZ12kP7zYIl4WN3ECdkQjKeL5UpnZasVmRuNb+oZzQ= Received: from skull.home.blih.net (ip-9.net-89-3-105.rev.numericable.fr [89.3.105.9]) by mail.blih.net (OpenSMTPD) with ESMTPSA id 1250cabc TLS version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO; Sun, 19 Aug 2018 12:29:07 +0200 (CEST) Date: Sun, 19 Aug 2018 12:29:07 +0200 From: Emmanuel Vadot To: Daniel Braniss Cc: Ian Lepore , Rajesh Kumar , freebsd-hackers@freebsd.org, freebsd-drivers@freebsd.org Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD Message-Id: <20180819122907.8c9306a0a307b9887443e818@bidouilliste.com> In-Reply-To: <3C2D99A1-DC1C-4915-81DE-7F9D48AAB10E@cs.huji.ac.il> References: <1534523216.27158.17.camel@freebsd.org> <3C2D99A1-DC1C-4915-81DE-7F9D48AAB10E@cs.huji.ac.il> X-Mailer: Sylpheed 3.7.0 (GTK+ 2.24.32; amd64-portbld-freebsd12.0) Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 19 Aug 2018 10:29:17 -0000 On Sun, 19 Aug 2018 13:11:15 +0300 Daniel Braniss wrote: >=20 >=20 > > On 17 Aug 2018, at 19:26, Ian Lepore wrote: > >=20 > > On Fri, 2018-08-17 at 11:48 +0530, Rajesh Kumar wrote: > >> Hi, > >>=20 > >> I am trying to use the I2C designware controller driver available in > >> FreeBSD (ig4_iic.c) in our boards. > >>=20 > >> Is there a clean way, I can set the I2C bus frequency from the control= ler > >> driver itself, rather than using device hints, FDT, tunables etc., > >> Something like, if the driver is loaded for our boards (identified usi= ng > >> the PCI or ACPI ID's), then the frequency of the I2C bus needs to be > >> hardcoded from driver itself. This is to avoid additional configs from= the > >> config file. > >>=20 > >> I tried adding a new interface "iicbus_set_frequency" (in line with > >> iicbus_get_frequency) and tried calling that from the ig4 driver after= the > >> "iicbus" child is added. But, iicbus instance is created only after i= g4 > >> driver is loaded. So, calling iicbus_set_frequency after child addition > >> leads to system panic (as there is no iicbus softc at this point). > >>=20 > >> Let me know if you need any details. > >>=20 > >> Thanks, > >> Rajesh. > >=20 > > I don't really understand what you're asking for. The ig4_iic > > controller driver doesn't appear to support bus frequency settings at > > all, it just loads hard-coded values into the clock high/low registers > > and never changes them. If you want to locally modify the driver to run > > at a different hard-coded speed for your application, just change lines > > 589-592 in ig4_iic.c and continue to ignore the speed set by the bus > > driver when handling iicbus_reset. > >=20 >=20 > on the arm/allwinner it?s set at 100Khz, and though there are sysctls to = change it, > it?s ignored :-) It is set at whatever frequency the dts set it and if there is no frequency in the dts it fallback to 100Khz. twsi needs to support IICBUS_GET_FREQUENCY though, the main reason I never really touched twsi is because the same driver is used on Marvell SoC with hackish support for the clocks. Now that I have a Marvell board with this i2c controller I'll probably rewrite this driver. > I could change this, but is there some hidden reason that it?s so? >=20 > danny >=20 > _______________________________________________ > freebsd-hackers@freebsd.org mailing list > https://lists.freebsd.org/mailman/listinfo/freebsd-hackers > To unsubscribe, send any mail to "freebsd-hackers-unsubscribe@freebsd.org" --=20 Emmanuel Vadot From owner-freebsd-drivers@freebsd.org Sun Aug 19 13:53:36 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id A98CC1066771; Sun, 19 Aug 2018 13:53:36 +0000 (UTC) (envelope-from rajfbsd@gmail.com) Received: from mail-wm0-x236.google.com (mail-wm0-x236.google.com [IPv6:2a00:1450:400c:c09::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 0B5D376EEE; Sun, 19 Aug 2018 13:53:36 +0000 (UTC) (envelope-from rajfbsd@gmail.com) Received: by mail-wm0-x236.google.com with SMTP id t25-v6so11329249wmi.3; Sun, 19 Aug 2018 06:53:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Tl40/EUx5fzuQv/rqv+5h+VYXB9PemqtD9b3O0nk/pQ=; b=eDzoFkodc/6D893yCUxhK8ybPFMTtaU02TAAS1QlUjdn5iIGuFOwluHC0cfyN7DyI5 AyBap6QMMLM1Vfm4aURYnDX6QE1mrRNYs5RHHKTA9p7qGT4ydtFZj8oYiBGksOwhIeYw +LITdxOUJtFuv6qIMsKfPybcuE05/jyc/WrG0NOD4U9cn+626rkW7XuGFkzD8ws2uil1 uU0uo9MnkhLRPawZ85FbQomz+OMKTcQRrEGp0MNNnWd832ktpITkPd/kmex2Im5DQtJd qJIjDD9YTJZWIlQLeQanidA6oj0jKt11DsnyRNG21guuTk3ZJaqFpogjFVWl7Fun7bm7 GLAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Tl40/EUx5fzuQv/rqv+5h+VYXB9PemqtD9b3O0nk/pQ=; b=pbukGbnPspQwAOgcr2LHyQvI7SUYkxEeDYot6zHNekQEhUos2U/wNgR86/w2NTABBV psHXtSFaUadFNSSYW3SeSTvAgcA8ug0cZHvrSR4ucR22Yd3xxg3ggV2h15FR8+VPQ6Ud cOMxCQ5MnJP9T+hZdhOYLqFcY2nd9TPNNVcX1AID9wxMHuIjwm7Tczx2vc92HLPqk9Bv TR/yQTeTgeji5aWlZlkPDy+7dS3VfVjWlvrBt+MIq6yzLju8NT8ysrVTZv8t1D6ANhnK UQYFhdxi10WYOsSxtn+mQPKaO1iOXvebYAa8eaz/n/1trV/IfQ08svKX4CAhaomUtWw6 zgSw== X-Gm-Message-State: AOUpUlGt/LUvt5lEi6J1Q5Tt67EcKDMbzArTtDvwJZiZYnFef73U9kgV 8LgfsdfcPSiEYdcO1O7ZhPfCm4VH5oNwkhoOySncgRVq X-Google-Smtp-Source: AA+uWPzYXEqCZzoIki6qiLKXdUSbi58MP8lDO7JWyoS9164ezednUTwuGMiKexfalthuOwvvZjM7BmYGH8ggBjP//mQ= X-Received: by 2002:a1c:20cb:: with SMTP id g194-v6mr24514815wmg.102.1534686814907; Sun, 19 Aug 2018 06:53:34 -0700 (PDT) MIME-Version: 1.0 References: <1534523216.27158.17.camel@freebsd.org> In-Reply-To: <1534523216.27158.17.camel@freebsd.org> From: Rajesh Kumar Date: Sun, 19 Aug 2018 19:23:22 +0530 Message-ID: Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD To: ian@freebsd.org Cc: freebsd-drivers@freebsd.org, freebsd-hackers@freebsd.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.27 X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 19 Aug 2018 13:53:36 -0000 Hi Ian, Basically, I want to set the I2C clock frequency for Designware IP in our board to 150Mhz. So, I was looking for the way in FreeBSD. So, Is this the frequency which is configured through the clock high/low registers? I see the those register are coded to 100 and 125 currently, I am not sure how that value is arrived. If it needs to be configured for 150Mhz, how to derive the appropriate values? I looked at the DW_apb_i2c databook section 3.11 to understand about it. I am still unclear. I see a comment saying "Program based on 25000 Hz clock". In my case, should they be programmed based on 150Mhz clock? On Fri, Aug 17, 2018 at 9:57 PM Ian Lepore wrote: > On Fri, 2018-08-17 at 11:48 +0530, Rajesh Kumar wrote: > > Hi, > > > > I am trying to use the I2C designware controller driver available in > > FreeBSD (ig4_iic.c) in our boards. > > > > Is there a clean way, I can set the I2C bus frequency from the controller > > driver itself, rather than using device hints, FDT, tunables etc., > > Something like, if the driver is loaded for our boards (identified using > > the PCI or ACPI ID's), then the frequency of the I2C bus needs to be > > hardcoded from driver itself. This is to avoid additional configs from > the > > config file. > > > > I tried adding a new interface "iicbus_set_frequency" (in line with > > iicbus_get_frequency) and tried calling that from the ig4 driver after > the > > "iicbus" child is added. But, iicbus instance is created only after ig4 > > driver is loaded. So, calling iicbus_set_frequency after child addition > > leads to system panic (as there is no iicbus softc at this point). > > > > Let me know if you need any details. > > > > Thanks, > > Rajesh. > > I don't really understand what you're asking for. The ig4_iic > controller driver doesn't appear to support bus frequency settings at > all, it just loads hard-coded values into the clock high/low registers > and never changes them. If you want to locally modify the driver to run > at a different hard-coded speed for your application, just change lines > 589-592 in ig4_iic.c and continue to ignore the speed set by the bus > driver when handling iicbus_reset. > > -- Ian > From owner-freebsd-drivers@freebsd.org Sun Aug 19 13:57:57 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 68E051066EAB; Sun, 19 Aug 2018 13:57:57 +0000 (UTC) (envelope-from rajfbsd@gmail.com) Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id DD9EB77329; Sun, 19 Aug 2018 13:57:56 +0000 (UTC) (envelope-from rajfbsd@gmail.com) Received: by mail-wr1-x42d.google.com with SMTP id o37-v6so1942896wrf.6; Sun, 19 Aug 2018 06:57:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=FzlduWxM+dE2pirXFru4a6RmI4DSYPVhkI0/7f4dXgw=; b=Y8hADueHuZJz397yAoUWbIgZB/neK1kt5t/Myj4Z1/Rspv0xAc/kZq/ly9FG4TwxwB BCxxGzEXqj57dr6arAwSt0a8TvOOcfdarkbPN+TTdFQBvSvD3w8j4YHs1BjEFulPI5Z9 AIE7OlYdlaB0J+vXZ1251EN3KJ4l87yaJ15gQYQblVeC/xjmPtH3YCOVDpDV8pXpKXvK tXGuCDnQEUSoRe8pg/SSxPeC7Ju4hz5ALU6gXU3qVeuaZFo4NOjKY7WefC9d2LeX6cEa 9cLZJMUFUrDjkUvCcoXwjyrhEdNg6yIYR6+y5nwQuS2wbPIMIrO6C7g9lSfdg7ORmL0h qbFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=FzlduWxM+dE2pirXFru4a6RmI4DSYPVhkI0/7f4dXgw=; b=AX8BzSOHaCQVDPjYx+czZGRmHBzRfZwUI73Iv+k9/YQGR7WhyEmHEF3fAjzqBeFZoy XZtnKrvpt+hiqpshefo+VBD1KkyfPCz1zGP1pkTqIrXcUkmY0KamXqPjgZYtc8lbXF2V VDO25BzajaITSHJ+D8CHicsPlY1X8zSeyOWm9VzNzWYPpPPda9SpqB0s04JcFCNOnbC3 0/6Isc2e5RA8tJwo7FsuUSECDR3+fkb42Grb3pDEGpd9OPLny050eVPpZHdU+BkPrv1j IZP3+bUoIPyJfTHs+lHA6xCTtPQCIxjUS8veoF7MLCnJ3D03QPaRB4uW2k1W5dv102J4 mITQ== X-Gm-Message-State: APzg51AohbOyuKrusUIAD6fJwsOxDJ6eDhxJsa0JaM5uF1aNxbUcxZxs zbZg2PmPcZb+An+hXC66D1upYHXE1K5ZlcwXCSk= X-Google-Smtp-Source: ANB0VdaHjQDC7f8yNsL+g563JQVEVM8agkpvkT5HY9NuPEy76ipowdvaywibeIzvXLTQC8LQ1dMhzUQOLq+UcDzKuRA= X-Received: by 2002:adf:ad34:: with SMTP id p49-v6mr6219503wrc.10.1534687075891; Sun, 19 Aug 2018 06:57:55 -0700 (PDT) MIME-Version: 1.0 References: <1534523216.27158.17.camel@freebsd.org> <3C2D99A1-DC1C-4915-81DE-7F9D48AAB10E@cs.huji.ac.il> <20180819122907.8c9306a0a307b9887443e818@bidouilliste.com> In-Reply-To: <20180819122907.8c9306a0a307b9887443e818@bidouilliste.com> From: Rajesh Kumar Date: Sun, 19 Aug 2018 19:27:44 +0530 Message-ID: Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD To: manu@bidouilliste.com Cc: danny@cs.huji.ac.il, ian@freebsd.org, freebsd-hackers@freebsd.org, freebsd-drivers@freebsd.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.27 X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 19 Aug 2018 13:57:57 -0000 Hi Daniel/Emmanuel, Basically, I want to set the I2C clock frequency for Designware IP in our board to 150Mhz. So, I was looking for the way in FreeBSD. Is this 100Khz in arm/allwinner is same as what I am trying to configure? Or Is it something different? On Sun, Aug 19, 2018 at 3:59 PM Emmanuel Vadot wrote: > On Sun, 19 Aug 2018 13:11:15 +0300 > Daniel Braniss wrote: > > > > > > > > On 17 Aug 2018, at 19:26, Ian Lepore wrote: > > > > > > On Fri, 2018-08-17 at 11:48 +0530, Rajesh Kumar wrote: > > >> Hi, > > >> > > >> I am trying to use the I2C designware controller driver available in > > >> FreeBSD (ig4_iic.c) in our boards. > > >> > > >> Is there a clean way, I can set the I2C bus frequency from the > controller > > >> driver itself, rather than using device hints, FDT, tunables etc., > > >> Something like, if the driver is loaded for our boards (identified > using > > >> the PCI or ACPI ID's), then the frequency of the I2C bus needs to be > > >> hardcoded from driver itself. This is to avoid additional configs > from the > > >> config file. > > >> > > >> I tried adding a new interface "iicbus_set_frequency" (in line with > > >> iicbus_get_frequency) and tried calling that from the ig4 driver > after the > > >> "iicbus" child is added. But, iicbus instance is created only after > ig4 > > >> driver is loaded. So, calling iicbus_set_frequency after child > addition > > >> leads to system panic (as there is no iicbus softc at this point). > > >> > > >> Let me know if you need any details. > > >> > > >> Thanks, > > >> Rajesh. > > > > > > I don't really understand what you're asking for. The ig4_iic > > > controller driver doesn't appear to support bus frequency settings at > > > all, it just loads hard-coded values into the clock high/low registers > > > and never changes them. If you want to locally modify the driver to run > > > at a different hard-coded speed for your application, just change lines > > > 589-592 in ig4_iic.c and continue to ignore the speed set by the bus > > > driver when handling iicbus_reset. > > > > > > > on the arm/allwinner it?s set at 100Khz, and though there are sysctls to > change it, > > it?s ignored :-) > > It is set at whatever frequency the dts set it and if there is no > frequency in the dts it fallback to 100Khz. > twsi needs to support IICBUS_GET_FREQUENCY though, the main reason I > never really touched twsi is because the same driver is used on Marvell > SoC with hackish support for the clocks. Now that I have a Marvell > board with this i2c controller I'll probably rewrite this driver. > > > I could change this, but is there some hidden reason that it?s so? > > > > danny > > > > _______________________________________________ > > freebsd-hackers@freebsd.org mailing list > > https://lists.freebsd.org/mailman/listinfo/freebsd-hackers > > To unsubscribe, send any mail to " > freebsd-hackers-unsubscribe@freebsd.org" > > > -- > Emmanuel Vadot > From owner-freebsd-drivers@freebsd.org Sun Aug 19 18:21:11 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 80E6B10734E3 for ; Sun, 19 Aug 2018 18:21:11 +0000 (UTC) (envelope-from ian@freebsd.org) Received: from outbound2r.ore.mailhop.org (outbound2r.ore.mailhop.org [54.200.129.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 108B4839EB for ; Sun, 19 Aug 2018 18:21:10 +0000 (UTC) (envelope-from ian@freebsd.org) X-MHO-RoutePath: aGlwcGll X-MHO-User: a0c63aca-a3dc-11e8-904b-1d2e466b3c59 X-Report-Abuse-To: https://support.duocircle.com/support/solutions/articles/5000540958-duocircle-standard-smtp-abuse-information X-Originating-IP: 67.177.211.60 X-Mail-Handler: DuoCircle Outbound SMTP Received: from ilsoft.org (unknown [67.177.211.60]) by outbound2.ore.mailhop.org (Halon) with ESMTPSA id a0c63aca-a3dc-11e8-904b-1d2e466b3c59; Sun, 19 Aug 2018 18:21:02 +0000 (UTC) Received: from rev (rev [172.22.42.240]) by ilsoft.org (8.15.2/8.15.2) with ESMTP id w7JIL1Od086042; Sun, 19 Aug 2018 12:21:01 -0600 (MDT) (envelope-from ian@freebsd.org) Message-ID: <1534702861.27158.36.camel@freebsd.org> Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD From: Ian Lepore To: Rajesh Kumar Cc: freebsd-drivers@freebsd.org, freebsd-hackers@freebsd.org Date: Sun, 19 Aug 2018 12:21:01 -0600 In-Reply-To: References: <1534523216.27158.17.camel@freebsd.org> Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.18.5.1 FreeBSD GNOME Team Port Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 19 Aug 2018 18:21:11 -0000 On Sun, 2018-08-19 at 19:23 +0530, Rajesh Kumar wrote: > Hi Ian, > > Basically, I want to set the I2C clock frequency for Designware IP in our > board to 150Mhz.  So, I was looking for the way in FreeBSD. > > So, Is this the frequency which is configured through the clock high/low > registers? I see the those register are coded to 100 and 125 currently, I > am not sure how that value is arrived. If it needs to be configured for > 150Mhz, how to derive the appropriate values? I looked at the DW_apb_i2c > databook section 3.11 to understand about it.  I am still unclear.  I see a > comment saying "Program based on 25000 Hz clock". In my case, should they > be programmed based on 150Mhz clock? Rajesh, Please bottom-post when replying on freebsd mailing lists, mixed top- and bottom-posting is too confusing. What exactly do you mean when you say "the i2c clock frequency"? The datasheet appears to use a term like that to refer to the internal clock used to drive the IP block in the chip. That base clock is then divided down to create the i2c bus frequency on the I2C_SCL line. The IG4_REG_SS_SCL_HCNT and IG4_REG_SS_SCL_LCNT registers are the duration in base clock ticks that the SCL line is held high and low for standard speed. The registers with FS in the name are for high speed mode. The comment block and the values our driver programs into those registers appear to be wildly wrong. There is no way a base clock running at 25KHz can be divided down to create i2c bus speeds of 100KHz and 400KHz for standard and fast modes. If the base clock really is 25KHz then the driver currently sets the i2c bus to run at 111Hz. The hardware default values for the HCNT/LCNT registers, as given in the datasheet referenced by the driver [1], would be consistant with an internal base clock speed of 1GHz. The fact that the header file defines a IG4_REG_CLK_PARMS register, but the datasheet doesn't mention it, makes me think that on some versions of the hardware the speed is fixed and the driver has to know what that is based on the version, or vendor, or something. Other versions of the hardware may have information about the base clock speed in that IG4_REG_CLK_PARMS register. What we need is for someone who has this hardware to put an oscilliscope on the SCL line and get us some real-world truth. [1] http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family-mobile-i-o-datasheet.html?wapkw=datasheets+4th+generation -- Ian From owner-freebsd-drivers@freebsd.org Mon Aug 20 06:49:34 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 0F3961086445; Mon, 20 Aug 2018 06:49:34 +0000 (UTC) (envelope-from danny@cs.huji.ac.il) Received: from kabab.cs.huji.ac.il (kabab.cs.huji.ac.il [132.65.116.210]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 11A347E40D; Mon, 20 Aug 2018 06:49:32 +0000 (UTC) (envelope-from danny@cs.huji.ac.il) Received: from bach.cs.huji.ac.il ([132.65.80.20]) by kabab.cs.huji.ac.il with esmtp id 1fre0D-000FYp-EW; Mon, 20 Aug 2018 09:49:25 +0300 From: Daniel Braniss Message-Id: Mime-Version: 1.0 (Mac OS X Mail 11.5 \(3445.9.1\)) Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD Date: Mon, 20 Aug 2018 09:49:25 +0300 In-Reply-To: <1534702861.27158.36.camel@freebsd.org> Cc: Rajesh Kumar , freebsd-hackers@freebsd.org, freebsd-drivers@freebsd.org To: Ian Lepore References: <1534523216.27158.17.camel@freebsd.org> <1534702861.27158.36.camel@freebsd.org> X-Mailer: Apple Mail (2.3445.9.1) Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.27 X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Aug 2018 06:49:35 -0000 > On 19 Aug 2018, at 21:21, Ian Lepore wrote: >=20 > On Sun, 2018-08-19 at 19:23 +0530, Rajesh Kumar wrote: >> Hi Ian, >>=20 >> Basically, I want to set the I2C clock frequency for Designware IP in = our >> board to 150Mhz. So, I was looking for the way in FreeBSD. >>=20 >> So, Is this the frequency which is configured through the clock = high/low >> registers? I see the those register are coded to 100 and 125 = currently, I >> am not sure how that value is arrived. If it needs to be configured = for >> 150Mhz, how to derive the appropriate values? I looked at the = DW_apb_i2c >> databook section 3.11 to understand about it. I am still unclear. I = see a >> comment saying "Program based on 25000 Hz clock". In my case, should = they >> be programmed based on 150Mhz clock? >=20 > Rajesh, >=20 > Please bottom-post when replying on freebsd mailing lists, mixed top- > and bottom-posting is too confusing. >=20 > What exactly do you mean when you say "the i2c clock frequency"? >=20 > The datasheet appears to use a term like that to refer to the internal > clock used to drive the IP block in the chip. That base clock is then > divided down to create the i2c bus frequency on the I2C_SCL line. >=20 > The IG4_REG_SS_SCL_HCNT and IG4_REG_SS_SCL_LCNT registers are the > duration in base clock ticks that the SCL line is held high and low = for > standard speed. The registers with FS in the name are for high speed > mode. >=20 > The comment block and the values our driver programs into those > registers appear to be wildly wrong. There is no way a base clock > running at 25KHz can be divided down to create i2c bus speeds of = 100KHz > and 400KHz for standard and fast modes. If the base clock really is > 25KHz then the driver currently sets the i2c bus to run at 111Hz. >=20 > The hardware default values for the HCNT/LCNT registers, as given in > the datasheet referenced by the driver [1], would be consistant with = an > internal base clock speed of 1GHz. The fact that the header file > defines a IG4_REG_CLK_PARMS register, but the datasheet doesn't = mention > it, makes me think that on some versions of the hardware the speed is > fixed and the driver has to know what that is based on the version, or > vendor, or something. Other versions of the hardware may have > information about the base clock speed in that IG4_REG_CLK_PARMS > register. >=20 > What we need is for someone who has this hardware to put an > oscilliscope on the SCL line and get us some real-world truth. >=20 > [1] = http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family= -mobile-i-o-datasheet.html?wapkw=3Ddatasheets+4th+generation = >=20 > -- Ian hi, I have similar issues with the allwinner/twsi but I do have a Saleae = Logic and here is a nice picture: danny From owner-freebsd-drivers@freebsd.org Mon Aug 20 08:13:17 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 41DA6108853E; Mon, 20 Aug 2018 08:13:17 +0000 (UTC) (envelope-from danny@cs.huji.ac.il) Received: from kabab.cs.huji.ac.il (kabab.cs.huji.ac.il [132.65.116.210]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id B30E68119A; Mon, 20 Aug 2018 08:13:16 +0000 (UTC) (envelope-from danny@cs.huji.ac.il) Received: from bach.cs.huji.ac.il ([132.65.80.20]) by kabab.cs.huji.ac.il with esmtp id 1frfJE-000OzS-LO; Mon, 20 Aug 2018 11:13:08 +0300 From: Daniel Braniss Message-Id: Mime-Version: 1.0 (Mac OS X Mail 11.5 \(3445.9.1\)) Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD Date: Mon, 20 Aug 2018 11:13:08 +0300 In-Reply-To: Cc: Rajesh Kumar , freebsd-hackers@freebsd.org, freebsd-drivers@freebsd.org To: Ian Lepore References: <1534523216.27158.17.camel@freebsd.org> <1534702861.27158.36.camel@freebsd.org> X-Mailer: Apple Mail (2.3445.9.1) Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.27 X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Aug 2018 08:13:17 -0000 > On 20 Aug 2018, at 09:49, Daniel Braniss wrote: >=20 >=20 >=20 >> On 19 Aug 2018, at 21:21, Ian Lepore > wrote: >>=20 >> On Sun, 2018-08-19 at 19:23 +0530, Rajesh Kumar wrote: >>> Hi Ian, >>>=20 >>> Basically, I want to set the I2C clock frequency for Designware IP = in our >>> board to 150Mhz. So, I was looking for the way in FreeBSD. >>>=20 >>> So, Is this the frequency which is configured through the clock = high/low >>> registers? I see the those register are coded to 100 and 125 = currently, I >>> am not sure how that value is arrived. If it needs to be configured = for >>> 150Mhz, how to derive the appropriate values? I looked at the = DW_apb_i2c >>> databook section 3.11 to understand about it. I am still unclear. = I see a >>> comment saying "Program based on 25000 Hz clock". In my case, should = they >>> be programmed based on 150Mhz clock? >>=20 >> Rajesh, >>=20 >> Please bottom-post when replying on freebsd mailing lists, mixed top- >> and bottom-posting is too confusing. >>=20 >> What exactly do you mean when you say "the i2c clock frequency"? >>=20 >> The datasheet appears to use a term like that to refer to the = internal >> clock used to drive the IP block in the chip. That base clock is then >> divided down to create the i2c bus frequency on the I2C_SCL line. >>=20 >> The IG4_REG_SS_SCL_HCNT and IG4_REG_SS_SCL_LCNT registers are the >> duration in base clock ticks that the SCL line is held high and low = for >> standard speed. The registers with FS in the name are for high speed >> mode. >>=20 >> The comment block and the values our driver programs into those >> registers appear to be wildly wrong. There is no way a base clock >> running at 25KHz can be divided down to create i2c bus speeds of = 100KHz >> and 400KHz for standard and fast modes. If the base clock really is >> 25KHz then the driver currently sets the i2c bus to run at 111Hz. >>=20 >> The hardware default values for the HCNT/LCNT registers, as given in >> the datasheet referenced by the driver [1], would be consistant with = an >> internal base clock speed of 1GHz. The fact that the header file >> defines a IG4_REG_CLK_PARMS register, but the datasheet doesn't = mention >> it, makes me think that on some versions of the hardware the speed is >> fixed and the driver has to know what that is based on the version, = or >> vendor, or something. Other versions of the hardware may have >> information about the base clock speed in that IG4_REG_CLK_PARMS >> register. >>=20 >> What we need is for someone who has this hardware to put an >> oscilliscope on the SCL line and get us some real-world truth. >>=20 >> [1] = http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family= -mobile-i-o-datasheet.html?wapkw=3Ddatasheets+4th+generation = > >>=20 >> -- Ian >=20 >=20 > hi, > I have similar issues with the allwinner/twsi but I do have a Saleae = Logic and here is a nice picture: ah, maybe this is better: = https://cs.huji.ac.il/~danny/Screen%20Shot%202018-08-20%20at%2011.06.43.pn= g >=20 >=20 >=20 > danny >=20 > _______________________________________________ > freebsd-hackers@freebsd.org = mailing list > https://lists.freebsd.org/mailman/listinfo/freebsd-hackers = > To unsubscribe, send any mail to = "freebsd-hackers-unsubscribe@freebsd.org = " From owner-freebsd-drivers@freebsd.org Mon Aug 20 09:36:40 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 5562E108A238; Mon, 20 Aug 2018 09:36:40 +0000 (UTC) (envelope-from rajfbsd@gmail.com) Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id A95D283BD9; Mon, 20 Aug 2018 09:36:39 +0000 (UTC) (envelope-from rajfbsd@gmail.com) Received: by mail-wr1-x432.google.com with SMTP id w11-v6so9827202wrc.5; Mon, 20 Aug 2018 02:36:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=zJ9dgvfPjlgToL3w7dMe1B+r0GyzSNSc6AasKP49K9M=; b=tSCdRKYr4FujycVqYGmM8Xq7xDquGKwnxfMP2z58c9UBIpTSQg159h2w2s8Zg8D35h kUY2c+kfOra4KA+WqUi773BGZEXF6K1Fgv7dlzv1yRCJvt+hrcAzimt88xCZuXoYSchh AsdrC/8HWWXblLQfeY3SwYfZ1wNWP2iDNSU2ot/6U+yo/wTgSWhQh3RyQxd80FeVJGFA qZAE4u2p+bYbOsZqhthgIIfvUC2AUs4cQ+LXVsLcYGWmxDVdiWWifBTYFaouem9Fjiky jhtfV2rTuyOqZ1zc/P7pvljaY146raaJshOXyBV2yt+bXT0+L2J0g9sg5/3/0ophAXGj 3Q9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=zJ9dgvfPjlgToL3w7dMe1B+r0GyzSNSc6AasKP49K9M=; b=RTd3iq8+SuKmu1yrvDq79pwW3IZIbicmw/CbJMjWdVWcvAteT1e8RXlzAzkJl+eG9V 7xlSGFW6nGtHISkmuJnS5oLKq2tznx4IuN0KtcJXKRWU3yZExQ9JzpQvw+dyc2zgtLjM nSYuory5UbXgf2TZSoTqkBSFrpsqbyOjJIG0AJyKtJTjE+rZb9KXTahYYB1wA0e/rTg1 5FGv86eXUg+PI4Nt7BUsyVFiopXiBZi+0NRLhvEj1QdSpJWjVNZHaijP9GZ3Qt7oHlfI pAZ74jspnqFHN/JL8vqBoeLTwZj2cDhC196+LwZHU/gxJS1q1qc+Z+tTVZzc/3rlQtVx 2bqw== X-Gm-Message-State: AOUpUlGEV3u2eNS6dcdNp8doPYBd5ud4LE9zrg7nxKEPrfiwkxd+WKd8 36zfgzHzuCY54U6+j/ZmQ0ISzsutDaZb6uxNZwLYU7dlttk= X-Google-Smtp-Source: AA+uWPzvzByWn93L0gHXE5ADN1KhxIsv9oxLAYDo1iuau/cBrDWDN0jk6t5tw4fP2ug3BJOC2BLG1o/OmZ3z1Eu1alU= X-Received: by 2002:adf:cc83:: with SMTP id p3-v6mr10754968wrj.226.1534757798586; Mon, 20 Aug 2018 02:36:38 -0700 (PDT) MIME-Version: 1.0 References: <1534523216.27158.17.camel@freebsd.org> <1534702861.27158.36.camel@freebsd.org> In-Reply-To: From: Rajesh Kumar Date: Mon, 20 Aug 2018 15:06:26 +0530 Message-ID: Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD To: danny@cs.huji.ac.il Cc: ian@freebsd.org, freebsd-hackers@freebsd.org, freebsd-drivers@freebsd.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.27 X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Aug 2018 09:36:40 -0000 Hi Ian/Daniel, Sorry about the mixed-posting. By "i2c clock frequency", I mean the internal base frequency only, which drives the chip. I thought data will be transferred on bus based on the base frequency. So, thought both bus and base frequency are same. But from what you said, seems both are different. So, based on the setting in *_HCNT/LCNT register, the bus frequency (which is the rate at which data is transferred) will change for a particular base frequency. Is that right? So, few questions here 1) As you said, we need to have a base frequency of 150 Mhz in our case. So, do we need to program that IG4_REG_CLK_PARMS to 150 Mhz (0x8F0D180)? And can this be done at the same time when programming the HCNT/LNCT registers? 2) Not sure how that 111Hz value is arrived. Can you please explain this calculation. So, that I can derive the appropriate values for HCNT/LCNT for different speeds at 150Mhz base clock. 3) "Default HCNT/LCNT register values would be consistent with an internal base clock speed of 1GHz", Does it mean with those values, all speeds can be achieved until 1GHz clock? 4) I am quite unfamiliar with the oscilloscope outputs. So, it would be good if you give some idea about what is shown in that pic? On Mon, Aug 20, 2018 at 1:43 PM Daniel Braniss wrote: > > > On 20 Aug 2018, at 09:49, Daniel Braniss wrote: > > > > On 19 Aug 2018, at 21:21, Ian Lepore wrote: > > On Sun, 2018-08-19 at 19:23 +0530, Rajesh Kumar wrote: > > Hi Ian, > > Basically, I want to set the I2C clock frequency for Designware IP in our > board to 150Mhz. So, I was looking for the way in FreeBSD. > > So, Is this the frequency which is configured through the clock high/low > registers? I see the those register are coded to 100 and 125 currently, I > am not sure how that value is arrived. If it needs to be configured for > 150Mhz, how to derive the appropriate values? I looked at the DW_apb_i2c > databook section 3.11 to understand about it. I am still unclear. I see a > comment saying "Program based on 25000 Hz clock". In my case, should they > be programmed based on 150Mhz clock? > > > Rajesh, > > Please bottom-post when replying on freebsd mailing lists, mixed top- > and bottom-posting is too confusing. > > What exactly do you mean when you say "the i2c clock frequency"? > > The datasheet appears to use a term like that to refer to the internal > clock used to drive the IP block in the chip. That base clock is then > divided down to create the i2c bus frequency on the I2C_SCL line. > > The IG4_REG_SS_SCL_HCNT and IG4_REG_SS_SCL_LCNT registers are the > duration in base clock ticks that the SCL line is held high and low for > standard speed. The registers with FS in the name are for high speed > mode. > > The comment block and the values our driver programs into those > registers appear to be wildly wrong. There is no way a base clock > running at 25KHz can be divided down to create i2c bus speeds of 100KHz > and 400KHz for standard and fast modes. If the base clock really is > 25KHz then the driver currently sets the i2c bus to run at 111Hz. > > The hardware default values for the HCNT/LCNT registers, as given in > the datasheet referenced by the driver [1], would be consistant with an > internal base clock speed of 1GHz. The fact that the header file > defines a IG4_REG_CLK_PARMS register, but the datasheet doesn't mention > it, makes me think that on some versions of the hardware the speed is > fixed and the driver has to know what that is based on the version, or > vendor, or something. Other versions of the hardware may have > information about the base clock speed in that IG4_REG_CLK_PARMS > register. > > What we need is for someone who has this hardware to put an > oscilliscope on the SCL line and get us some real-world truth. > > [1] > http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family-mobile-i-o-datasheet.html?wapkw=datasheets+4th+generation > < > http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family-mobile-i-o-datasheet.html?wapkw=datasheets+4th+generation > > > > -- Ian > > > > hi, > I have similar issues with the allwinner/twsi but I do have a Saleae Logic > and here is a nice picture: > > > ah, maybe this is better: > https://cs.huji.ac.il/~danny/Screen%20Shot%202018-08-20%20at%2011.06.43.png > > > > > danny > > _______________________________________________ > freebsd-hackers@freebsd.org mailing list > https://lists.freebsd.org/mailman/listinfo/freebsd-hackers > To unsubscribe, send any mail to "freebsd-hackers-unsubscribe@freebsd.org" > > > From owner-freebsd-drivers@freebsd.org Mon Aug 20 13:18:20 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 5AC12106D84B for ; Mon, 20 Aug 2018 13:18:20 +0000 (UTC) (envelope-from ian@freebsd.org) Received: from outbound2r.ore.mailhop.org (outbound2r.ore.mailhop.org [54.200.129.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id D71CA8C9D6 for ; Mon, 20 Aug 2018 13:18:19 +0000 (UTC) (envelope-from ian@freebsd.org) X-MHO-RoutePath: aGlwcGll X-MHO-User: 7f1764d8-a47b-11e8-904b-1d2e466b3c59 X-Report-Abuse-To: https://support.duocircle.com/support/solutions/articles/5000540958-duocircle-standard-smtp-abuse-information X-Originating-IP: 67.177.211.60 X-Mail-Handler: DuoCircle Outbound SMTP Received: from ilsoft.org (unknown [67.177.211.60]) by outbound2.ore.mailhop.org (Halon) with ESMTPSA id 7f1764d8-a47b-11e8-904b-1d2e466b3c59; Mon, 20 Aug 2018 13:18:17 +0000 (UTC) Received: from rev (rev [172.22.42.240]) by ilsoft.org (8.15.2/8.15.2) with ESMTP id w7KDIFgW087893; Mon, 20 Aug 2018 07:18:15 -0600 (MDT) (envelope-from ian@freebsd.org) Message-ID: <1534771095.27158.46.camel@freebsd.org> Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD From: Ian Lepore To: Daniel Braniss Cc: Rajesh Kumar , freebsd-hackers@freebsd.org, freebsd-drivers@freebsd.org Date: Mon, 20 Aug 2018 07:18:15 -0600 In-Reply-To: References: <1534523216.27158.17.camel@freebsd.org> <1534702861.27158.36.camel@freebsd.org> Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.18.5.1 FreeBSD GNOME Team Port Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Aug 2018 13:18:20 -0000 On Mon, 2018-08-20 at 11:13 +0300, Daniel Braniss wrote: > > > > > On 20 Aug 2018, at 09:49, Daniel Braniss wrote: > > > > > > > > > > > > On 19 Aug 2018, at 21:21, Ian Lepore wrote: > > > > > > On Sun, 2018-08-19 at 19:23 +0530, Rajesh Kumar wrote: > > > > > > > > Hi Ian, > > > > > > > > Basically, I want to set the I2C clock frequency for Designware IP in our > > > > board to 150Mhz.  So, I was looking for the way in FreeBSD. > > > > > > > > So, Is this the frequency which is configured through the clock high/low > > > > registers? I see the those register are coded to 100 and 125 currently, I > > > > am not sure how that value is arrived. If it needs to be configured for > > > > 150Mhz, how to derive the appropriate values? I looked at the DW_apb_i2c > > > > databook section 3.11 to understand about it.  I am still unclear.  I see a > > > > comment saying "Program based on 25000 Hz clock". In my case, should they > > > > be programmed based on 150Mhz clock? > > > Rajesh, > > > > > > Please bottom-post when replying on freebsd mailing lists, mixed top- > > > and bottom-posting is too confusing. > > > > > > What exactly do you mean when you say "the i2c clock frequency"? > > > > > > The datasheet appears to use a term like that to refer to the internal > > > clock used to drive the IP block in the chip. That base clock is then > > > divided down to create the i2c bus frequency on the I2C_SCL line. > > > > > > The IG4_REG_SS_SCL_HCNT and IG4_REG_SS_SCL_LCNT registers are the > > > duration in base clock ticks that the SCL line is held high and low for > > > standard speed. The registers with FS in the name are for high speed > > > mode. > > > > > > The comment block and the values our driver programs into those > > > registers appear to be wildly wrong. There is no way a base clock > > > running at 25KHz can be divided down to create i2c bus speeds of 100KHz > > > and 400KHz for standard and fast modes. If the base clock really is > > > 25KHz then the driver currently sets the i2c bus to run at 111Hz. > > > > > > The hardware default values for the HCNT/LCNT registers, as given in > > > the datasheet referenced by the driver [1], would be consistant with an > > > internal base clock speed of 1GHz. The fact that the header file > > > defines a IG4_REG_CLK_PARMS register, but the datasheet doesn't mention > > > it, makes me think that on some versions of the hardware the speed is > > > fixed and the driver has to know what that is based on the version, or > > > vendor, or something. Other versions of the hardware may have > > > information about the base clock speed in that IG4_REG_CLK_PARMS > > > register. > > > > > > What we need is for someone who has this hardware to put an > > > oscilliscope on the SCL line and get us some real-world truth. > > > > > > [1] http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family-mobile-i-o-datasheet.html?wapkw=datasheets+4th+generation > > > > > > > -- Ian > > > > hi, > > I have similar issues with the allwinner/twsi but I do have a Saleae Logic and here is a nice picture: > ah, maybe this is better: > https://cs.huji.ac.il/~danny/Screen%20Shot%202018-08-20%20at%2011.06.43.png > > > > > > > > > > danny This has nothing to do with the twsi driver, this is about the ig4 driver (found in sys/dev/ichiic). That screenshot seems to show a bus running at 100KHz like it should (although the 62:38 duty cycle is a bit suspicious). -- Ian From owner-freebsd-drivers@freebsd.org Mon Aug 20 14:16:29 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 9FEC6106F02B for ; Mon, 20 Aug 2018 14:16:29 +0000 (UTC) (envelope-from marklmi26-fbsd@yahoo.com) Received: from sonic316-8.consmr.mail.gq1.yahoo.com (sonic316-8.consmr.mail.gq1.yahoo.com [98.137.69.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 213E68EB8E for ; Mon, 20 Aug 2018 14:16:28 +0000 (UTC) (envelope-from marklmi26-fbsd@yahoo.com) X-YMail-OSG: VGq812IVM1lkSSyCICS7JNpmc08qdmmUfRq9G_L.SPS2B9B.jtpgvnkryc5ddAp JvYr3TraqG1AP3Q8V0JxHlcltE1JQPQubTmqx5gREabq3vEiG_TKLWLvvS2cOpQkkkNAbvzXOxSg zIX4gzbJnCwauF5z8dFaDMm_BacpoQsFOrPb4VTeflr8tjgD3TrPGJf1_XHEUFu71t0d.V_HhSCv 9H7M55XBSyfoReBDvA2wTcAVNC.5xwnjOYxfcfp7m1iWAjv_nt63aAd.NoiVqRMxbxKDWZz.mmRW cVayd3nA4PQ7blrOU.3RBpydF8H_jYVCXPvSFtho_mGDc0TYCj6nuxf8kluYYvW_ZyKCI1vbE5D1 lWKAxvBUHIzf1n5phUAkVGNMMndCR7rcGXVeN8rex2YGZu7zjhZUU9uoN4Ox9uM3MfHNo9vYgMxP icNEqi4PDCDPnCMLY6DYMKMAR3AmLwwIiTUr.Fd0CbQCtMUxUCKiW1uOsYrTL7tt2QbndGTsR7Ku hQBX1LrcT5Do95TD_0LVG_RXxi4KQ2atypjUbidNGY_VUu15IVxPfFAGMfHkQ1xK4jYyoVLab_f9 5jWBPqyoScfQzPkGcq4dyuqpD.xgzgyZeOmNxTMJZVohZ3pDAMS0jgqafiNLtb4ONBBSRT9ABinp f3q03VQehflY3GLsvosamJ_0.n19KRF48CfTwVeQQmWymENjMB7E2kBLv9yai584Qn_YinvzQXmi k0.hIboCNSEqqptBzKQZc1Xcl6oa5mbiJMxHmaf8q27UXVFZHUwOIOC8S8HcCc8aGeVnz6YnpMFu gTGMFtbKF7D_kv.ZpzMjGzyDOjGbdqV21aqRVLuiwNCft78vmcdjeuCvnwdBDtsJiLcC4skzuulW tqJS7hQuH3nB4bVTDxXWkAb.Aa5EWbQqdUqOHqHdhrPIE5U.H.mC07CUpcQ5q6wWyZaYgQ2io7xK ssHgeN.HaEncVIHb_nXj5AT_CTOCdCZwp3qJdWOKGhkqbbzYkSFfYpSMjhFO.ILU3Dwf8esUOcjZ ZKGiKurJ8 Received: from sonic.gate.mail.ne1.yahoo.com by sonic316.consmr.mail.gq1.yahoo.com with HTTP; Mon, 20 Aug 2018 14:16:21 +0000 Received: from ip70-189-131-151.lv.lv.cox.net (EHLO [192.168.0.105]) ([70.189.131.151]) by smtp410.mail.gq1.yahoo.com (Oath Hermes SMTP Server) with ESMTPA ID d257edfd13b2bed4706d68af7d4e1a91; Mon, 20 Aug 2018 14:16:18 +0000 (UTC) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 11.5 \(3445.9.1\)) Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD From: Mark Millard In-Reply-To: <1534771095.27158.46.camel@freebsd.org> Date: Mon, 20 Aug 2018 07:16:15 -0700 Cc: Ian Lepore , Rajesh Kumar , Toomas Soome via freebsd-hackers , freebsd-drivers@freebsd.org Content-Transfer-Encoding: quoted-printable Message-Id: <35F2C250-B4CB-4C53-BF8F-43C338022E34@yahoo.com> References: <1534523216.27158.17.camel@freebsd.org> <1534702861.27158.36.camel@freebsd.org> <1534771095.27158.46.camel@freebsd.org> To: Daniel Braniss X-Mailer: Apple Mail (2.3445.9.1) X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Aug 2018 14:16:29 -0000 On 2018-Aug-20, at 6:18 AM, Ian Lepore wrote: > On Mon, 2018-08-20 at 11:13 +0300, Daniel Braniss wrote: >>=20 >>>=20 >>> On 20 Aug 2018, at 09:49, Daniel Braniss = wrote: >>>=20 >>>> . . . >>>=20 >>> hi, >>> I have similar issues with the allwinner/twsi but I do have a Saleae = Logic and here is a nice picture: >> ah, maybe this is better: >> = https://cs.huji.ac.il/~danny/Screen%20Shot%202018-08-20%20at%2011.06.43.pn= g > . . . > This has nothing to do with the twsi driver, this is about the ig4 > driver (found in sys/dev/ichiic). >=20 > That screenshot seems to show a bus running at 100KHz like it should > (although the 62:38 duty cycle is a bit suspicious). Being a logic analyzer display, it my just be that the threshold was off from the optimal value. The waveform shape is not really visible. The logic analyzer output also shows a thick "rising" edge without the uparrow symbol. My guess would be that is a rising/falling/rising sequence that on the scale in use does not show space between edges. In other words: a glitch on the leading edge side of the intended pulse. This too might be tied to the threshold used vs . the actual signal properties: no way to tell from what is shown. =3D=3D=3D Mark Millard marklmi at yahoo.com ( dsl-only.net went away in early 2018-Mar) From owner-freebsd-drivers@freebsd.org Mon Aug 20 16:00:23 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 6CEA810734D2 for ; Mon, 20 Aug 2018 16:00:23 +0000 (UTC) (envelope-from marklmi@yahoo.com) Received: from sonic315-13.consmr.mail.bf2.yahoo.com (sonic315-13.consmr.mail.bf2.yahoo.com [74.6.134.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 1518773D85 for ; Mon, 20 Aug 2018 16:00:22 +0000 (UTC) (envelope-from marklmi@yahoo.com) X-YMail-OSG: uwn8u18VM1leMvAyyZrxR2bwiVUsTeA6Otq1iyo30byDwzlYi_UyJSeTgxIV3NZ diRU85xcQeM.Ucnr6k9rRkvr9RE9UUd5PxZ21cZ8B08YsHogLVkjFZl404F1mgY2SIUJoBnuTXuo f5FrS7zpuIbBf_HyYOzLcAGix7eRuJHt6119Gh4C1w24_.Srg2oBRKcVl.4JJkNE2q0X7SWSvhGi G9rvZp6f4rxo_bE527YIOwgZHe6G0b7DBZAQH4OBhM09IufiaChH9oc8j4D1j8KwRKdnsq_Rf.QB p9vyMGX91lRZqbPZ1C5J1Kw7sulMHAhFTgv.7t_eFGQmOtpOY5VNlplvFD.PEa5tvc6kkYIwebQa o0tBSwlWunrc4aodrQIfBAd1WsSGVlBQ8h_OLKn._91GNwz1iGLnyOJlzpg1C03OQg.q3UEu9CCn ds7zMWQ.PKREWnhLcfu6wnt.Y_sF_TUZufRb4SVbipkfyvaWPxe4UN9iwUFm0yaqaC9fB1D0c36I QA3Yg1zWUwdhtJKqCvwKUlc9qV1NFNTc0s5RQccp66kzoIV9BYtdFPiTvz3ueBWngxxgkef_1sOy 9NpsiY_B4uxsxg7gKlD48z2RxmnAp2Trx9bKXFI68rPY.mrEptRhVx_3L474rjG5FloChoyMMLiL 49506nsWA7ySz_.R_IyRBHSbImMsoMV63KIK0SnYRUz0niPr_A0U4C4Hfn0k__NkyQAP2pF8ExuH SKd4XEvy561VP3dir0L0.QcVB44nlQFVnCkCX.cGGWEY4XMikOrRnP4bAUwAsbRpOW2GCQcpCHG7 mZqKUy5g5.KoZd5PHnHmcIyKuJMNJ1OpX1sZ8OuDv24eCdwEGb9nDwjbep5fVQlq4l2AxOxDE1FZ lCKz3NOA0wz0COlNjunTCBUqaz849szXY_3fKOO1JymTQeVwQxZ.Pebbn23cluXaEIRnxy1wvl00 jaAEluIiGEQCSCiAwcdXKrvOoRchGAABBNIuoZonXWWd_N3tyqNgJG1acwRXFNIWnjGoNhrK3wNc DF1.bW3U6YuJ1.w-- Received: from sonic.gate.mail.ne1.yahoo.com by sonic315.consmr.mail.bf2.yahoo.com with HTTP; Mon, 20 Aug 2018 16:00:22 +0000 Received: from ip70-189-131-151.lv.lv.cox.net (EHLO [192.168.0.105]) ([70.189.131.151]) by smtp422.mail.bf1.yahoo.com (Oath Hermes SMTP Server) with ESMTPA ID 218f368d65d3a390e5ff3d4a5d591849; Mon, 20 Aug 2018 16:00:19 +0000 (UTC) From: Mark Millard Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Mime-Version: 1.0 (Mac OS X Mail 11.5 \(3445.9.1\)) Subject: Fwd: Need a clarification regarding I2C bus frequency in FreeBSD Message-Id: References: <35F2C250-B4CB-4C53-BF8F-43C338022E34@yahoo.com> To: Toomas Soome via freebsd-hackers , freebsd-drivers@freebsd.org Date: Mon, 20 Aug 2018 09:00:17 -0700 X-Mailer: Apple Mail (2.3445.9.1) X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Aug 2018 16:00:23 -0000 [Resend to (just the list) from the right account.] On 2018-Aug-20, at 6:18 AM, Ian Lepore wrote: > On Mon, 2018-08-20 at 11:13 +0300, Daniel Braniss wrote: >>=20 >>>=20 >>> On 20 Aug 2018, at 09:49, Daniel Braniss = wrote: >>>=20 >>>> . . . >>>=20 >>> hi, >>> I have similar issues with the allwinner/twsi but I do have a Saleae = Logic and here is a nice picture: >> ah, maybe this is better: >> = https://cs.huji.ac.il/~danny/Screen%20Shot%202018-08-20%20at%2011.06.43.pn= g > . . . > This has nothing to do with the twsi driver, this is about the ig4 > driver (found in sys/dev/ichiic). >=20 > That screenshot seems to show a bus running at 100KHz like it should > (although the 62:38 duty cycle is a bit suspicious). Being a logic analyzer display, it my just be that the threshold was off from the optimal value. The waveform shape is not really visible. The logic analyzer output also shows a thick "rising" edge without the uparrow symbol. My guess would be that is a rising/falling/rising sequence that on the scale in use does not show space between edges. In other words: a glitch on the leading edge side of the intended pulse. This too might be tied to the threshold used vs . the actual signal properties: no way to tell from what is shown. =3D=3D=3D Mark Millard marklmi at yahoo.com ( dsl-only.net went away in early 2018-Mar) From owner-freebsd-drivers@freebsd.org Mon Aug 20 16:13:26 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 146C510740C0; Mon, 20 Aug 2018 16:13:26 +0000 (UTC) (envelope-from gljennjohn@gmail.com) Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 7FB1C74CA2; Mon, 20 Aug 2018 16:13:25 +0000 (UTC) (envelope-from gljennjohn@gmail.com) Received: by mail-wr1-x433.google.com with SMTP id 20-v6so7478363wrb.12; Mon, 20 Aug 2018 09:13:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:in-reply-to:references:reply-to :mime-version:content-transfer-encoding; bh=EhIAyQi9LHZZPtsr7XHJC6XfyavYw2vT5mKQJMunLlY=; b=lneuZs+1G7Q9chxqt73PHcBKL2d8Me5p5AHJJ2u30Zsb+SbGpC+kwwZohod04DEIpH mtbV9+yxrP/0VTfUzoPrxqEhbu8SSARTnGXFp2wZbRV/TmOoviHnTG96YWVBdref6jkX gpDNBDERGK3jYKmPlosXvCbk3YZ/13ddYXXNffuxRcYSngM75Op60VMNL/58DlX6imYK hqtlf1JixgibVAcHWK898QPl1Pcne+Ym3Q3+aHzNu3DGeFwDgbT8stBca1CfQ3eMLBp0 7ciXxaBAdYpfN11Yr131sRqUrj6YYmgXS5YooXdPuqY0sJBkvhbp9dIWrtgYAvW9bRUq rFLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:reply-to:mime-version:content-transfer-encoding; bh=EhIAyQi9LHZZPtsr7XHJC6XfyavYw2vT5mKQJMunLlY=; b=ocWU2+pxazlVY8gBjkatiMBKU3OSRO5Y2WhHBhhtxQICwSJQFZb1A0nyG23VOq6bOV jLnKuVK3Y3hB+5pQQ2F5gBx6JxDe7YGBgMEYqFIhBhpZ16POcPaIwO2xLcK3I1ZmJ1hY a/+dXMrMnBtYg7FiZ0EBkAp/Qs5oodZvd25+XgECa1Db0Jjaqwb3Dlc2PqjI3AL266cp t7Y0l9jSrEYXx/cNFheBh96UEEojM/YXUc1ow9ZULtS2h3L4kHwhlHKwZLzYOiGFCORa 2GHnkHxOBWLvAWaWj6WMbEf81lmx3BYkYUD5F3KmdhA16hCeOI2TZWzqgiWg2RFvaWc/ Ef2w== X-Gm-Message-State: APzg51Dqxup3DuBO5LP+ib8+0/sRhxcHedseAtzV7ktd8aTkAq7HaHuH HxOjgS6rJOJVNkaqHtS6SLLaS3W0 X-Google-Smtp-Source: ANB0Vdbg8CMI1qWrwS7hxKfJrdKK03e28zbYVCrqJ+rIAGvcUR4lF7KMdm4E3hNJAgx5LrBWgMoy3A== X-Received: by 2002:adf:f7c4:: with SMTP id a4-v6mr5620416wrq.86.1534781604370; Mon, 20 Aug 2018 09:13:24 -0700 (PDT) Received: from ernst.home (p5B0234D5.dip0.t-ipconnect.de. [91.2.52.213]) by smtp.gmail.com with ESMTPSA id y128-v6sm12203wmy.26.2018.08.20.09.13.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 20 Aug 2018 09:13:23 -0700 (PDT) Date: Mon, 20 Aug 2018 18:13:22 +0200 From: Gary Jennejohn To: Mark Millard via freebsd-hackers Cc: Mark Millard , Daniel Braniss , Rajesh Kumar , freebsd-drivers@freebsd.org, Ian Lepore Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD Message-ID: <20180820181322.71607854@ernst.home> In-Reply-To: <35F2C250-B4CB-4C53-BF8F-43C338022E34@yahoo.com> References: <1534523216.27158.17.camel@freebsd.org> <1534702861.27158.36.camel@freebsd.org> <1534771095.27158.46.camel@freebsd.org> <35F2C250-B4CB-4C53-BF8F-43C338022E34@yahoo.com> Reply-To: gljennjohn@gmail.com X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; amd64-portbld-freebsd12.0) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Aug 2018 16:13:26 -0000 On Mon, 20 Aug 2018 07:16:15 -0700 Mark Millard via freebsd-hackers wrote: > On 2018-Aug-20, at 6:18 AM, Ian Lepore wrote: > > > On Mon, 2018-08-20 at 11:13 +0300, Daniel Braniss wrote: > >> > >>> > >>> On 20 Aug 2018, at 09:49, Daniel Braniss wrote: > >>> > >>>> . . . > >>> > >>> hi, > >>> I have similar issues with the allwinner/twsi but I do have a Saleae Logic and here is a nice picture: > >> ah, maybe this is better: > >> https://cs.huji.ac.il/~danny/Screen%20Shot%202018-08-20%20at%2011.06.43.png > > . . . > > This has nothing to do with the twsi driver, this is about the ig4 > > driver (found in sys/dev/ichiic). > > > > That screenshot seems to show a bus running at 100KHz like it should > > (although the 62:38 duty cycle is a bit suspicious). > > Being a logic analyzer display, it my just be that the threshold > was off from the optimal value. The waveform shape is not really > visible. > > The logic analyzer output also shows a thick "rising" edge without the > uparrow symbol. My guess would be that is a rising/falling/rising > sequence that on the scale in use does not show space between edges. In > other words: a glitch on the leading edge side of the intended pulse. > This too might be tied to the threshold used vs . the actual signal > properties: no way to tell from what is shown. > I have two of these logic analyzers and they definitely do a major clean up of the signals displayed. Things like overshoot and ringing, which can be seen on an oscilloscope, do not appear on what the logic analyzer displays. I suspect the purpose of the trace was simply to show the 100KHz SCL. -- Gary Jennejohn From owner-freebsd-drivers@freebsd.org Mon Aug 20 17:55:47 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 958DB1077780; Mon, 20 Aug 2018 17:55:47 +0000 (UTC) (envelope-from rajfbsd@gmail.com) Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id E916179C90; Mon, 20 Aug 2018 17:55:46 +0000 (UTC) (envelope-from rajfbsd@gmail.com) Received: by mail-wr1-x429.google.com with SMTP id g1-v6so13707153wru.2; Mon, 20 Aug 2018 10:55:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=wwOZv/9aHCETh455mFE3Lwr8S/NgRDPtK1ctk83xZkA=; b=RKU1d00zOIz2kVOKdWYy//8BIhYYWbn+Qh1JKzkTeqQVf17j4q7jkc5PgkNnjmUiHG 3JPODSKGlWwcMD+nrnSl7o9oWL8W6/4cVoGwDrfCDKFr9EGsHalr3nOX1kZrnQ7mI+Tm uLak9QQJk1sRjn59BshOpMaJKNGiFIxvShgKSFmE4LIXzMksvLQIdHv27fOTGHFgJM4t 2lkhZ3lq001nJbAVYT8Y9DVlTANsgHhFF/C+X17fTumzjgJCogh4sUiq22wMHokH86A8 pvlbHIJ+u+dPr7N6d9WLdE6c1pXirUAvWlykjvmh5CkfgCMQesPGCgPb/ZnJct9z7B1P 5liQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wwOZv/9aHCETh455mFE3Lwr8S/NgRDPtK1ctk83xZkA=; b=MqFi8po3Jdl6zHhVLcoBEbbIcn+1q8qINduQuiffJZZ9WpLiJ5TqVXP1NlTPmWPbZ0 0LaZ3puLZXggQ0PShkE47n4iEDCndEAYn7whH7QHSeT+X6ovpA7jYSKa/uswK4/OQP5B JR3v3RLcuJQRw0Dk063kcszlisULu523u2ofDqYjo0+ZiYYKJKbQJCifDyDuO0yDIW24 Bb12TB8dcmdWpvJfmfW2jdLWDRHcXDjNR/fdxGubp/yzOqENPT9jx7BSESNJOwTTS5dV lmLxL6iVNc5h99OdA9qutaXzNy8hvVXTS4Vot0xKtPWE/ZNL+GuyyPhMl5xXIjWh36Bc zAeA== X-Gm-Message-State: APzg51A8g5H7oaoL0hJ74T8AB8FOQp+GMXi7GRTiR9Tqp4W353d47G/2 Vr0+wb7bbzX06Uh45lBYgowIjy+88UBeuuv0FhA= X-Google-Smtp-Source: ANB0Vda51o0Gqizdmb5km/8PzXw6gWpRxDQCWrfnJHizNqAjRurhH3iYCzcClMYJUBuvi5lhSzPa79Cj8Ihh7Y46IXg= X-Received: by 2002:a5d:4152:: with SMTP id c18-v6mr5119203wrq.61.1534787745172; Mon, 20 Aug 2018 10:55:45 -0700 (PDT) MIME-Version: 1.0 References: <1534523216.27158.17.camel@freebsd.org> <1534702861.27158.36.camel@freebsd.org> <1534771095.27158.46.camel@freebsd.org> <35F2C250-B4CB-4C53-BF8F-43C338022E34@yahoo.com> <20180820181322.71607854@ernst.home> In-Reply-To: <20180820181322.71607854@ernst.home> From: Rajesh Kumar Date: Mon, 20 Aug 2018 23:25:33 +0530 Message-ID: Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD To: gljennjohn@gmail.com Cc: freebsd-hackers@freebsd.org, marklmi26-fbsd@yahoo.com, danny@cs.huji.ac.il, freebsd-drivers@freebsd.org, ian@freebsd.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.27 X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Aug 2018 17:55:47 -0000 Hi, Re-posting the questions, just in case if its missed in other conversation. By "i2c clock frequency", I mean the internal base frequency only, which drives the chip. I thought data will be transferred on bus based on the base frequency. So, thought both bus and base frequency are same. But from what you said, seems both are different. So, based on the setting in *_HCNT/LCNT register, the bus frequency (which is the rate at which data is transferred) will change for a particular base frequency. Is that right? So, few questions here 1) As you said, we need to have a base frequency of 150 Mhz in our case. So, do we need to program that IG4_REG_CLK_PARMS to 150 Mhz (0x8F0D180)? And can this be done at the same time when programming the HCNT/LNCT registers? 2) Not sure how that 111Hz value is arrived. Can you please explain this calculation. So, that I can derive the appropriate values for HCNT/LCNT for different speeds at 150Mhz base clock. 3) "Default HCNT/LCNT register values would be consistent with an internal base clock speed of 1GHz", Does it mean with those values, all speeds can be achieved until 1GHz clock? On Mon, Aug 20, 2018 at 9:43 PM Gary Jennejohn wrote: > On Mon, 20 Aug 2018 07:16:15 -0700 > Mark Millard via freebsd-hackers wrote: > > > On 2018-Aug-20, at 6:18 AM, Ian Lepore wrote: > > > > > On Mon, 2018-08-20 at 11:13 +0300, Daniel Braniss wrote: > > >> > > >>> > > >>> On 20 Aug 2018, at 09:49, Daniel Braniss > wrote: > > >>> > > >>>> . . . > > >>> > > >>> hi, > > >>> I have similar issues with the allwinner/twsi but I do have a Saleae > Logic and here is a nice picture: > > >> ah, maybe this is better: > > >> > https://cs.huji.ac.il/~danny/Screen%20Shot%202018-08-20%20at%2011.06.43.png > > > > . . . > > > This has nothing to do with the twsi driver, this is about the ig4 > > > driver (found in sys/dev/ichiic). > > > > > > That screenshot seems to show a bus running at 100KHz like it should > > > (although the 62:38 duty cycle is a bit suspicious). > > > > Being a logic analyzer display, it my just be that the threshold > > was off from the optimal value. The waveform shape is not really > > visible. > > > > The logic analyzer output also shows a thick "rising" edge without the > > uparrow symbol. My guess would be that is a rising/falling/rising > > sequence that on the scale in use does not show space between edges. In > > other words: a glitch on the leading edge side of the intended pulse. > > This too might be tied to the threshold used vs . the actual signal > > properties: no way to tell from what is shown. > > > > I have two of these logic analyzers and they definitely do a > major clean up of the signals displayed. > > Things like overshoot and ringing, which can be seen on an > oscilloscope, do not appear on what the logic analyzer displays. > > I suspect the purpose of the trace was simply to show the 100KHz > SCL. > > -- > Gary Jennejohn > From owner-freebsd-drivers@freebsd.org Tue Aug 21 05:14:29 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 63FE51089305; Tue, 21 Aug 2018 05:14:29 +0000 (UTC) (envelope-from danny@cs.huji.ac.il) Received: from kabab.cs.huji.ac.il (kabab.cs.huji.ac.il [132.65.116.210]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id C57B873104; Tue, 21 Aug 2018 05:14:28 +0000 (UTC) (envelope-from danny@cs.huji.ac.il) Received: from bach.cs.huji.ac.il ([132.65.80.20]) by kabab.cs.huji.ac.il with esmtp id 1fryzc-000NY9-Sb; Tue, 21 Aug 2018 08:14:12 +0300 From: Daniel Braniss Message-Id: <9F8E2C3D-61D6-487E-A19D-6B91FBAD930B@cs.huji.ac.il> Mime-Version: 1.0 (Mac OS X Mail 11.5 \(3445.9.1\)) Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD Date: Tue, 21 Aug 2018 08:14:11 +0300 In-Reply-To: <20180820181322.71607854@ernst.home> Cc: Mark Millard via freebsd-hackers , Mark Millard , Rajesh Kumar , freebsd-drivers@freebsd.org, Ian Lepore To: gljennjohn@gmail.com References: <1534523216.27158.17.camel@freebsd.org> <1534702861.27158.36.camel@freebsd.org> <1534771095.27158.46.camel@freebsd.org> <35F2C250-B4CB-4C53-BF8F-43C338022E34@yahoo.com> <20180820181322.71607854@ernst.home> X-Mailer: Apple Mail (2.3445.9.1) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.27 X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 21 Aug 2018 05:14:29 -0000 > On 20 Aug 2018, at 19:13, Gary Jennejohn wrote: >=20 > On Mon, 20 Aug 2018 07:16:15 -0700 > Mark Millard via freebsd-hackers > wrote: >=20 >> On 2018-Aug-20, at 6:18 AM, Ian Lepore wrote: >>=20 >>> On Mon, 2018-08-20 at 11:13 +0300, Daniel Braniss wrote: =20 >>>>=20 >>>>>=20 >>>>> On 20 Aug 2018, at 09:49, Daniel Braniss = wrote: >>>>>=20 >>>>>> . . . =20 >>>>>=20 >>>>> hi, >>>>> I have similar issues with the allwinner/twsi but I do have a = Saleae Logic and here is a nice picture: =20 >>>> ah, maybe this is better: >>>> = https://cs.huji.ac.il/~danny/Screen%20Shot%202018-08-20%20at%2011.06.43.pn= g =20 >>> . . . >>> This has nothing to do with the twsi driver, this is about the ig4 >>> driver (found in sys/dev/ichiic). >>>=20 >>> That screenshot seems to show a bus running at 100KHz like it should >>> (although the 62:38 duty cycle is a bit suspicious). =20 >>=20 >> Being a logic analyzer display, it my just be that the threshold >> was off from the optimal value. The waveform shape is not really >> visible. >>=20 >> The logic analyzer output also shows a thick "rising" edge without = the >> uparrow symbol. My guess would be that is a rising/falling/rising >> sequence that on the scale in use does not show space between edges. = In >> other words: a glitch on the leading edge side of the intended pulse. >> This too might be tied to the threshold used vs . the actual signal >> properties: no way to tell from what is shown. >>=20 >=20 > I have two of these logic analyzers and they definitely do a > major clean up of the signals displayed. >=20 > Things like overshoot and ringing, which can be seen on an > oscilloscope, do not appear on what the logic analyzer displays. >=20 > I suspect the purpose of the trace was simply to show the 100KHz > SCL. >=20 yup, I connected the logic analyzer to check the frequency, which was not changing, later I confirmed by looking at the source that it=E2=80= =99s set at a constant 100KHz. > --=20 > Gary Jennejohn From owner-freebsd-drivers@freebsd.org Tue Aug 21 06:06:58 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 57DCC108A50F; Tue, 21 Aug 2018 06:06:58 +0000 (UTC) (envelope-from rajfbsd@gmail.com) Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id D785A74ACD; Tue, 21 Aug 2018 06:06:57 +0000 (UTC) (envelope-from rajfbsd@gmail.com) Received: by mail-wr1-x42e.google.com with SMTP id m27-v6so8545819wrf.3; Mon, 20 Aug 2018 23:06:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=4NUAC4SG9ggVygxP698XPl3AI5sPHa+E/+91MyGNFRA=; b=es5JsmTmHPN2ySvUlIgEQXUFKPFx2TRXPTAW8vzLqQxduic+kOzHv8+HIxM1RvuPWU kMZo15pBBCxeLj6P9bDRe8+Cy64+y02m/a6bs85yu9cvfKZ7oomm2AKoZzkOeLB9/mYi jfDsbqBwmKHq1ejekys5vNXz7upkkEIFfbXBh4dKYr8eGkIaNHahZ9YK9KHDznvV5qwY DnbjVjFXWGLXDLiVFL+UtHxyfvWUkdWPDsObRLox1uXRv7qjW3a12bmL65G//4mL5PUS tljeMLRJ9ar4rWJEGL6DHMu1OdxTh92cRLuIk91FTgzIzNEEZkK2A7nF9vwznUcij2Uo rx9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=4NUAC4SG9ggVygxP698XPl3AI5sPHa+E/+91MyGNFRA=; b=TyCX9V1E3yapXCFXDmdN7+PyFEfARxIxXNNnYDC4w8EQyxl26KJUa/2ySd3Mud+13q E105iD3goVW5dhkxcsvoxvkBwqEQ/h+exbcB8X2tz79TgWn21EEqalgxBqB6UP6H2mWn 3CD1hiepUzqnFojZScZQFGVd2FVjP6kLUxrGyknvm4UO9x7E2fN5++TGmJFiQMq71dwp ozn/jPAd2a3J/iAly/NftfbFSPWiNtkGVT2SXopApcQv13Mky01TMC6+S77Hhi7q7vbW KEtLoM9PXXesqAKiA6cYEPTr6WGYY59Z7I74t6yLb2d9c6xPRbkZVvy13GWEWgtkqgiN jSkw== X-Gm-Message-State: APzg51DkCXFa6w0L0VH/j03cG5zjngvz2o4NRPwtodHSEse0acqBWMaL +Y/5l7YN0+qZRA2fQQ3nbdlJA/weBRnw1wuAj22udUdq X-Google-Smtp-Source: ANB0VdYlNSB4y5tqZnQHXmaxP7QrTAGN/pJ25WzI84IvRzmU1vvR78AQS5ab3VVnBKAz/z4QATz2SeXZrUv/r6VYjrE= X-Received: by 2002:adf:806d:: with SMTP id 100-v6mr7968538wrk.23.1534831616522; Mon, 20 Aug 2018 23:06:56 -0700 (PDT) MIME-Version: 1.0 From: Rajesh Kumar Date: Tue, 21 Aug 2018 11:36:44 +0530 Message-ID: Subject: Can we use INTRNG with amd64 platforms? To: freebsd-amd64@freebsd.org, freebsd-drivers@freebsd.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.27 X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 21 Aug 2018 06:06:58 -0000 Hi, I am writing a GPIO driver for a amd64 platform. I see an option INTRNG for GPIO interrupt handling in arm platforms. Can we use INTRNG in amd64 platform? I tried compiling freebsd with "options INTRNG" in amd64 platform, but it says "Unknown option INTRNG". So, Just wanted to clarify whether INTRNG is supported in amd64? If not, is there any equivalent available for amd64? Also, Is there any available document which explains about INTRNG features? From owner-freebsd-drivers@freebsd.org Tue Aug 21 14:33:09 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 936741074815 for ; Tue, 21 Aug 2018 14:33:09 +0000 (UTC) (envelope-from ian@freebsd.org) Received: from outbound2r.ore.mailhop.org (outbound2r.ore.mailhop.org [54.200.129.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 11FAF866E8 for ; Tue, 21 Aug 2018 14:33:08 +0000 (UTC) (envelope-from ian@freebsd.org) X-MHO-RoutePath: aGlwcGll X-MHO-User: 1aa19205-a54f-11e8-904b-1d2e466b3c59 X-Report-Abuse-To: https://support.duocircle.com/support/solutions/articles/5000540958-duocircle-standard-smtp-abuse-information X-Originating-IP: 67.177.211.60 X-Mail-Handler: DuoCircle Outbound SMTP Received: from ilsoft.org (unknown [67.177.211.60]) by outbound2.ore.mailhop.org (Halon) with ESMTPSA id 1aa19205-a54f-11e8-904b-1d2e466b3c59; Tue, 21 Aug 2018 14:33:01 +0000 (UTC) Received: from rev (rev [172.22.42.240]) by ilsoft.org (8.15.2/8.15.2) with ESMTP id w7LEX0Vo090677; Tue, 21 Aug 2018 08:33:00 -0600 (MDT) (envelope-from ian@freebsd.org) Message-ID: <1534861980.27158.145.camel@freebsd.org> Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD From: Ian Lepore To: Rajesh Kumar , gljennjohn@gmail.com Cc: freebsd-hackers@freebsd.org, freebsd-drivers@freebsd.org Date: Tue, 21 Aug 2018 08:33:00 -0600 In-Reply-To: References: <1534523216.27158.17.camel@freebsd.org> <1534702861.27158.36.camel@freebsd.org> <1534771095.27158.46.camel@freebsd.org> <35F2C250-B4CB-4C53-BF8F-43C338022E34@yahoo.com> <20180820181322.71607854@ernst.home> Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.18.5.1 FreeBSD GNOME Team Port Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 21 Aug 2018 14:33:09 -0000 On Mon, 2018-08-20 at 23:25 +0530, Rajesh Kumar wrote: > Hi, > > Re-posting the questions, just in case if its missed in other conversation. > > By "i2c clock frequency", I mean the internal base frequency only, which > drives the chip.  I thought data will be transferred on bus based on the > base frequency. So, thought both bus and base frequency are same. But from > what you said, seems both are different. So, based on the setting in > *_HCNT/LCNT register, the bus frequency (which is the rate at which data is > transferred) will change for a particular base frequency. Is that right? > > So, few questions here > > 1)  As you said, we need to have a base frequency of 150 Mhz in our case. > So, do we need to program that IG4_REG_CLK_PARMS to 150 Mhz (0x8F0D180)? > And can this be done at the same time when programming the HCNT/LNCT > registers? I don't have this hardware, and I don't have a datasheet that describes the IG4_REG_CLK_PARMS register mentioned in the driver, so I don't really have an answer. I suspect the hardware should set that register with information that lets the driver know what the base clock speed is. Using that information, the driver could calculate the proper values for HCNT/LCNT. Right now the driver lacks *any* support for changing bus speeds. That will be easy to fix, once we figure out:  1. What is in the IG4_REG_CLK_PARMS register?  2. What do we do about versions of the hardware that don't support that register?  > 2)  Not sure how that 111Hz value is arrived.  Can you please explain this > calculation. So, that I can derive the appropriate values for HCNT/LCNT for > different speeds at 150Mhz base clock. It's based on the comment (which I feel certain must be wrong) that the base clock is 25,000 Hz. With HCNT,LCNT set to 100,125, one cycle of the SCL line will last 225 base clock cycles. 1/25000 = 0.000040, that times 225 is 0.009 seconds per SCL cycle. 1/.009 = 111.111 Hz. FWIW, an i2c bus will run fine at 111Hz, it'll just take forever to get anything done. But I don't think the bus is really running at 111Hz, because I don't think the base clock is really 25KHz, I think the comment block is just wrong about all of that. > 3)  "Default HCNT/LCNT register values would be consistent with an internal > base clock speed of 1GHz",  Does it mean with those values, all speeds can > be achieved until 1GHz clock? > Well, the defaults I mentioned are from the datasheet cited in the driver code. Those defaults made me think the base clock was 1GHz on that particular hardware. I just realized that I was off by an order of magnitude, I think I was mixing numbers from the driver and numbers from the datasheet in my head.  The default HCNT,LCNT in that datasheet are 612+706=1318 base cycles to give an SCL rate of 100KHz. So 1318*100000 is 131.8MHz, a very reasonable number. In your world you want the 150MHz base clock to generate the 100Hz SCL, so 150000000/100000 = 1500. My inclination would be to split that in half and have HCNT,LCNT be 750,750, but for some reason there seems to be a bias on this hardware for having HCNT be slightly longer than LCNT, so maybe 775,725. Maybe that's an attempt to compensate for the fact that high levels on the clock line are accomplished with a pullup resistor, and it takes slightly longer for the line to "drift up" to a high state via the pullup, compared to being driven low which would happen quickly. I would expect the default values of the HCNT/LCNT registers would be right for any given hardware... whoever configures the IP block in a SoC would configure the base clock value and the default HCNT/LCNT values to match each other. Putting it that way makes me think that maybe the right thing to do in the driver is just stop setting HCNT/LCNT at all, and rely on the hardware to be configured correctly by default. It's worth a try. It would also be interesting to just print out those values. In the driver on lines 571-575 the code reads all those registers and does nothing with them. If you look in the dragonflybsd version of the driver it printed out all those values after reading them; whoever imported the driver to freebsd just deleted all the kprintf() lines and left the register reads. -- Ian From owner-freebsd-drivers@freebsd.org Tue Aug 21 15:16:30 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 58EAB1075AE9; Tue, 21 Aug 2018 15:16:30 +0000 (UTC) (envelope-from gljennjohn@gmail.com) Received: from mail-wm0-x234.google.com (mail-wm0-x234.google.com [IPv6:2a00:1450:400c:c09::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id BD28088872; Tue, 21 Aug 2018 15:16:29 +0000 (UTC) (envelope-from gljennjohn@gmail.com) Received: by mail-wm0-x234.google.com with SMTP id n11-v6so3194432wmc.2; Tue, 21 Aug 2018 08:16:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:in-reply-to:references:reply-to :mime-version:content-transfer-encoding; bh=pRJfUfmnb9jB351GNr/CKbKrfjnL2ToAhiTDO25n1vo=; b=VKnEqPCx3rTBDENrBFoF2Ar9miTutqIk4FD0+537jy0BxRAtcrHNtoNtdO2Tb5nf8G 90HdTQ83Ax9NoMCHvsEIR/L/i9/Fzz170P+udfmzghkCl7k62fysU7aZfsAMZV+uYg57 dfs7CYUcTsxbryXVt3S1FrrxoElIyPnhb7lV1jYYBiOsSPrSRFOQkvpLcBGSDjWTAhPm hgyABvtpoAqpAoJWVbkpArHJTs/Rgo06miAx6LPm4KLwGw0nGgB2ztalgwpA7vaJcj1X mQWBbt7gUqxdqFonJMKo2E46jo/UYdhSGQYkSZ8ZAG6WWeDq20MNXIEyBqw8Z91u51i8 LyZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:reply-to:mime-version:content-transfer-encoding; bh=pRJfUfmnb9jB351GNr/CKbKrfjnL2ToAhiTDO25n1vo=; b=Hn97J0xcTzFuxGSuNcKJlVO41I7kcUpvZq/IQVrsWMllQYEOghD9Oew3dH5dRMOQ/c Sedf2ckeURsxlFKJE3g7q32YaPSuPtK4h2+lWWqwRzNDY2OF7ELWT/pcchrsuh9EbmL+ vLy++6cS6MT7CqyydFFpDBKs98gUKRv4fIEIwf0wCNCLoaezUgH82I+UaJMReZ5CCuxT Udosm89yozszdzV2WFQCEb1UT+qY7nhirJMed6g0TpNooJcxT2YfTnNf6kz1nJVI2tT7 i76+2COztMOygcywpID4ernxNmsi6YqDOZJqHNZlM2eCQR6WXNQ7ft/P4fj1HT8b9yFn RjEA== X-Gm-Message-State: APzg51BhKMBzeIGZc4ReFdNgygtxtlDG6lYMJkT56ciwv/g9BFhbiyOe lQuo614vrbgMEDXV3vS7ZkfqLMvb X-Google-Smtp-Source: ANB0VdaPMuFxKxikOZR3bPowFK6gUMBlJpiYc89H17u8j3K37lXFyKTbSVH6nYz5jtFYxhX1ksvzlg== X-Received: by 2002:a1c:ea91:: with SMTP id g17-v6mr2519377wmi.65.1534864588525; Tue, 21 Aug 2018 08:16:28 -0700 (PDT) Received: from ernst.home (p5B02336E.dip0.t-ipconnect.de. [91.2.51.110]) by smtp.gmail.com with ESMTPSA id g133-v6sm3142828wmf.44.2018.08.21.08.16.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 21 Aug 2018 08:16:27 -0700 (PDT) Date: Tue, 21 Aug 2018 17:16:26 +0200 From: Gary Jennejohn To: Ian Lepore Cc: Rajesh Kumar , freebsd-hackers@freebsd.org, freebsd-drivers@freebsd.org Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD Message-ID: <20180821171626.49951728@ernst.home> In-Reply-To: <1534861980.27158.145.camel@freebsd.org> References: <1534523216.27158.17.camel@freebsd.org> <1534702861.27158.36.camel@freebsd.org> <1534771095.27158.46.camel@freebsd.org> <35F2C250-B4CB-4C53-BF8F-43C338022E34@yahoo.com> <20180820181322.71607854@ernst.home> <1534861980.27158.145.camel@freebsd.org> Reply-To: gljennjohn@gmail.com X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; amd64-portbld-freebsd12.0) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 21 Aug 2018 15:16:30 -0000 On Tue, 21 Aug 2018 08:33:00 -0600 Ian Lepore wrote: > On Mon, 2018-08-20 at 23:25 +0530, Rajesh Kumar wrote: > > Hi, > > > > Re-posting the questions, just in case if its missed in other conversation. > > > > By "i2c clock frequency", I mean the internal base frequency only, which > > drives the chip.____I thought data will be transferred on bus based on the > > base frequency. So, thought both bus and base frequency are same. But from > > what you said, seems both are different. So, based on the setting in > > *_HCNT/LCNT register, the bus frequency (which is the rate at which data is > > transferred) will change for a particular base frequency. Is that right? > > > > So, few questions here > > > > 1)____As you said, we need to have a base frequency of 150 Mhz in our case. > > So, do we need to program that IG4_REG_CLK_PARMS to 150 Mhz (0x8F0D180)? > > And can this be done at the same time when programming the HCNT/LNCT > > registers? > > I don't have this hardware, and I don't have a datasheet that describes > the__IG4_REG_CLK_PARMS register mentioned in the driver, so I don't > really have an answer. I suspect the hardware should set that register > with information that lets the driver know what the base clock speed > is. Using that information, the driver could calculate the proper > values for HCNT/LCNT. > > Right now the driver lacks *any* support for changing bus speeds. That > will be easy to fix, once we figure out: > > __1. What is in the IG4_REG_CLK_PARMS register? > __2. What do we do about versions of the hardware that don't support > that register?__ > > > 2)____Not sure how that 111Hz value is arrived.____Can you please explain this > > calculation. So, that I can derive the appropriate values for HCNT/LCNT for > > different speeds at 150Mhz base clock. > > It's based on the comment (which I feel certain must be wrong) that the > base clock is 25,000 Hz. With HCNT,LCNT set to 100,125, one cycle of > the SCL line will last 225 base clock cycles. 1/25000 = 0.000040, that > times 225 is 0.009 seconds per SCL cycle. 1/.009 = 111.111 Hz. > > FWIW, an i2c bus will run fine at 111Hz, it'll just take forever to get > anything done. But I don't think the bus is really running at 111Hz, > because I don't think the base clock is really 25KHz, I think the > comment block is just wrong about all of that. > > > 3)____"Default HCNT/LCNT register values would be consistent with an internal > > base clock speed of 1GHz",____Does it mean with those values, all speeds can > > be achieved until 1GHz clock? > > > > Well, the defaults I mentioned are from the datasheet cited in the > driver code. Those defaults made me think the base clock was 1GHz on > that particular hardware. I just realized that I was off by an order of > magnitude, I think I was mixing numbers from the driver and numbers > from the datasheet in my head. __The default HCNT,LCNT in that datasheet > are 612+706=1318 base cycles to give an SCL rate of 100KHz. So > 1318*100000 is 131.8MHz, a very reasonable number. > > In your world you want the 150MHz base clock to generate the 100Hz SCL, > so 150000000/100000 = 1500. My inclination would be to split that in > half and have HCNT,LCNT be 750,750, but for some reason there seems to > be a bias on this hardware for having HCNT be slightly longer than > LCNT, so maybe 775,725. Maybe that's an attempt to compensate for the > fact that high levels on the clock line are accomplished with a pullup > resistor, and it takes slightly longer for the line to "drift up" to a > high state via the pullup, compared to being driven low which would > happen quickly. > Just a remark. According to Table 10 in Chapter 6 of the I2C standard from NXP, SCL low must satisfy a minimum of 4.7 uS and SCL high must satisfy a minimum of 4.0 uS when running SCL at 100KHz. At 400KHz the values are respectively 1.3uS and 0.6uS. 725 results in 4.83uS, which would be OK for the low phase if it gets pulled low quite quickly. 775 results in 5.17uS, which is also acceptable, especially if it takes rather long for it to be pulled up. 750 results in 5.0uS for each, of course. This may theoreticalluy be a safer value, but it doesn't reflect any odd behavior which the real hardware may exhibit. > I would expect the default values of the HCNT/LCNT registers would be > right for any given hardware... whoever configures the IP block in a > SoC would configure the base clock value and the default HCNT/LCNT > values to match each other. Putting it that way makes me think that > maybe the right thing to do in the driver is just stop setting > HCNT/LCNT at all, and rely on the hardware to be configured correctly > by default. It's worth a try. > > It would also be interesting to just print out those values. In the > driver on lines 571-575 the code reads all those registers and does > nothing with them. If you look in the dragonflybsd version of the > driver it printed out all those values after reading them; whoever > imported the driver to freebsd just deleted all the kprintf() lines and > left the register reads. > -- Gary Jennejohn From owner-freebsd-drivers@freebsd.org Thu Aug 23 11:22:50 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 90E12108A7BF; Thu, 23 Aug 2018 11:22:50 +0000 (UTC) (envelope-from rajfbsd@gmail.com) Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id F0ABC8DE75; Thu, 23 Aug 2018 11:22:49 +0000 (UTC) (envelope-from rajfbsd@gmail.com) Received: by mail-wr1-x435.google.com with SMTP id a108-v6so4297687wrc.13; Thu, 23 Aug 2018 04:22:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=K0CCUDKUjPX78vxmx2ZMfgDUXgzP82QYi4td2QI4D3s=; b=QT/zidTcJB0xdkH5S67hk1RFPAOAkMdFubOMHC2Rc/JcecP/QTyYrKCi7BasiFAvZ2 M5vOcXSTdYyIqkr5qL+aiyv/q3iuVkwPJW67rhuAjWGtVjBpzXHQH9UGmbw1xKRFR3s3 sn1Zja2JdEn3vJRSpT8zf5WWhKC/hapLy9c7Js5PX3OsFcam8ed1S2c9wg+gjdCYU2lE gW1N+x+NsD/ZZjKeRuKapOEjzbH1+gcxnUu0FLRLRMtgwlj2l8VJTX9X9xf1i9zjYYCi 7/Gdhga3n6drU2KYYr36x+jkkNi2UzE2b+Ywk0SAhnpNUxlOFVP2Yox3G0/G9tRXMUUB skrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=K0CCUDKUjPX78vxmx2ZMfgDUXgzP82QYi4td2QI4D3s=; b=L6LxgZuUTWHaRnk+Zd/rsEFhJQskapHBPNgczXNMTWUXU2lqUKTYIS2CkyQ/UiwB+G BNMhjUkTgXfLJg+tbeQsknwi3jLBtbR56Y1zBkzGkgPX/4/DQAvrGKH+N2ie9p+8G9Ft gPx7Y7bcQZE+YH4CIaMkYuq0Gs5I0N98wFCmz9uYytmkqQgDdbfbF+TW4zonwHeKJYxa J27mNQ2xfFZKmJ0PrfPT8qpEfVvk8s190Zmm7nQGXHbHqv6md9Ee2SsGVuUUjw+jeZF9 pYcXNBKN8jkF9l3HGDLzkfw9ZnoMGUi2TYS5IWButBMrpbq6MSWQ2dJpsrpLdnA+87Fb xfbw== X-Gm-Message-State: APzg51BBbU/hdEzvMnj3qbw6LGx0nlevO6lFAIjQChOcJ0zwtls8eazL uWMvhcypbJftv4vPxopiqdKEfh/mXPPVoHMlb9TTDorx X-Google-Smtp-Source: ANB0VdZdfDnGzY5OnpNKqzEs69ryYd8Sg3TenDSPxJebFWJwE/8q1ijU/tvNuV3rfrL92x5OIIYYwszDpH3tSYWtZ/w= X-Received: by 2002:adf:806d:: with SMTP id 100-v6mr14504681wrk.23.1535023368497; Thu, 23 Aug 2018 04:22:48 -0700 (PDT) MIME-Version: 1.0 References: <1534523216.27158.17.camel@freebsd.org> <1534702861.27158.36.camel@freebsd.org> <1534771095.27158.46.camel@freebsd.org> <35F2C250-B4CB-4C53-BF8F-43C338022E34@yahoo.com> <20180820181322.71607854@ernst.home> <1534861980.27158.145.camel@freebsd.org> <20180821171626.49951728@ernst.home> In-Reply-To: <20180821171626.49951728@ernst.home> From: Rajesh Kumar Date: Thu, 23 Aug 2018 16:52:36 +0530 Message-ID: Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD To: gljennjohn@gmail.com Cc: ian@freebsd.org, freebsd-hackers@freebsd.org, freebsd-drivers@freebsd.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.27 X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Aug 2018 11:22:50 -0000 Hi Ian/Gary, Thanks for such a detailed explanation. It helps me understand some basics. > Right now the driver lacks *any* support for changing bus speeds. That > will be easy to fix, once we figure out: > > __1. What is in the IG4_REG_CLK_PARMS register? > __2. What do we do about versions of the hardware that don't support > that register?__ I tested with my hardware and it seems it doesn't have the IG4_REG_CLK_PARMS registers. When I try to read that offset, it's returning 0x63636363 (looks like some junk value?) Also, I don't see any register which specifies the base clock frequency directly, so that we can change the HCNT/LCNT as needed (which I belive you mean by changing the bus frequency here) > It would also be interesting to just print out those values. In the > driver on lines 571-575 the code reads all those registers and does > nothing with them. If you look in the dragonflybsd version of the > driver it printed out all those values after reading them; whoever > imported the driver to freebsd just deleted all the kprintf() lines and > left the register reads. I dumped few registers (during ig4iic_attach) and below are the details. Looks like in my case SS HCNT/LCNT default is 645/855 ( total - 1500). So, the base frequency seems to be configured to 150Mhz by default. Also, FS HCNT/LCNT default is 0x87/0xF0 (total - 375), which also proves the base frequency to be 150Mhz. So, my base requirement is satisfied. But, as I mentioned earlier, there is no direct way to get (or) configure the base frequency from the driver. IG4_REG_CTL 00000063 IG4_REG_SS_SCL_HCNT 00000285 IG4_REG_SS_SCL_LCNT 00000357 IG4_REG_FS_SCL_HCNT 00000087 IG4_REG_FS_SCL_LCNT 000000f0 IG4_REG_INTR_STAT 00000000 IG4_REG_INTR_MASK 00000000 IG4_REG_RAW_INTR_STAT 000000 IG4_REG_CLK_PARMS 63636363 IG4_REG_GENERAL 55555555 > According to Table 10 in Chapter 6 of the I2C standard from NXP, > SCL low must satisfy a minimum of 4.7 uS and SCL high must > satisfy a minimum of 4.0 uS when running SCL at 100KHz. At > 400KHz the values are respectively 1.3uS and 0.6uS. The above HCNT/LCNT numbers seems to match the minium requirements for SCL both in SS and FS case. Seems, this driver is written initially for controllers in Intel SoC's. Now, as we need this driver for other SoC's like in my case, can we generalize this driver by removing unnecessary checks for the "version" to be ATOM/HASWELL/SKYWELL/APL etc., If there is no concern regarding this, I will try to make the necessary changes. On Tue, Aug 21, 2018 at 8:46 PM Gary Jennejohn wrote: > On Tue, 21 Aug 2018 08:33:00 -0600 > Ian Lepore wrote: > > > On Mon, 2018-08-20 at 23:25 +0530, Rajesh Kumar wrote: > > > Hi, > > > > > > Re-posting the questions, just in case if its missed in other > conversation. > > > > > > By "i2c clock frequency", I mean the internal base frequency only, > which > > > drives the chip.____I thought data will be transferred on bus based on > the > > > base frequency. So, thought both bus and base frequency are same. But > from > > > what you said, seems both are different. So, based on the setting in > > > *_HCNT/LCNT register, the bus frequency (which is the rate at which > data is > > > transferred) will change for a particular base frequency. Is that > right? > > > > > > So, few questions here > > > > > > 1)____As you said, we need to have a base frequency of 150 Mhz in our > case. > > > So, do we need to program that IG4_REG_CLK_PARMS to 150 Mhz > (0x8F0D180)? > > > And can this be done at the same time when programming the HCNT/LNCT > > > registers? > > > > I don't have this hardware, and I don't have a datasheet that describes > > the__IG4_REG_CLK_PARMS register mentioned in the driver, so I don't > > really have an answer. I suspect the hardware should set that register > > with information that lets the driver know what the base clock speed > > is. Using that information, the driver could calculate the proper > > values for HCNT/LCNT. > > > > Right now the driver lacks *any* support for changing bus speeds. That > > will be easy to fix, once we figure out: > > > > __1. What is in the IG4_REG_CLK_PARMS register? > > __2. What do we do about versions of the hardware that don't support > > that register?__ > > > > > 2)____Not sure how that 111Hz value is arrived.____Can you please > explain this > > > calculation. So, that I can derive the appropriate values for > HCNT/LCNT for > > > different speeds at 150Mhz base clock. > > > > It's based on the comment (which I feel certain must be wrong) that the > > base clock is 25,000 Hz. With HCNT,LCNT set to 100,125, one cycle of > > the SCL line will last 225 base clock cycles. 1/25000 = 0.000040, that > > times 225 is 0.009 seconds per SCL cycle. 1/.009 = 111.111 Hz. > > > > FWIW, an i2c bus will run fine at 111Hz, it'll just take forever to get > > anything done. But I don't think the bus is really running at 111Hz, > > because I don't think the base clock is really 25KHz, I think the > > comment block is just wrong about all of that. > > > > > 3)____"Default HCNT/LCNT register values would be consistent with an > internal > > > base clock speed of 1GHz",____Does it mean with those values, all > speeds can > > > be achieved until 1GHz clock? > > > > > > > Well, the defaults I mentioned are from the datasheet cited in the > > driver code. Those defaults made me think the base clock was 1GHz on > > that particular hardware. I just realized that I was off by an order of > > magnitude, I think I was mixing numbers from the driver and numbers > > from the datasheet in my head. __The default HCNT,LCNT in that datasheet > > are 612+706=1318 base cycles to give an SCL rate of 100KHz. So > > 1318*100000 is 131.8MHz, a very reasonable number. > > > > In your world you want the 150MHz base clock to generate the 100Hz SCL, > > so 150000000/100000 = 1500. My inclination would be to split that in > > half and have HCNT,LCNT be 750,750, but for some reason there seems to > > be a bias on this hardware for having HCNT be slightly longer than > > LCNT, so maybe 775,725. Maybe that's an attempt to compensate for the > > fact that high levels on the clock line are accomplished with a pullup > > resistor, and it takes slightly longer for the line to "drift up" to a > > high state via the pullup, compared to being driven low which would > > happen quickly. > > > > Just a remark. > > According to Table 10 in Chapter 6 of the I2C standard from NXP, > SCL low must satisfy a minimum of 4.7 uS and SCL high must > satisfy a minimum of 4.0 uS when running SCL at 100KHz. At > 400KHz the values are respectively 1.3uS and 0.6uS. > > 725 results in 4.83uS, which would be OK for the low phase if it > gets pulled low quite quickly. 775 results in 5.17uS, which is > also acceptable, especially if it takes rather long for it to be > pulled up. > > 750 results in 5.0uS for each, of course. This may theoreticalluy > be a safer value, but it doesn't reflect any odd behavior which the > real hardware may exhibit. > > > I would expect the default values of the HCNT/LCNT registers would be > > right for any given hardware... whoever configures the IP block in a > > SoC would configure the base clock value and the default HCNT/LCNT > > values to match each other. Putting it that way makes me think that > > maybe the right thing to do in the driver is just stop setting > > HCNT/LCNT at all, and rely on the hardware to be configured correctly > > by default. It's worth a try. > > > > It would also be interesting to just print out those values. In the > > driver on lines 571-575 the code reads all those registers and does > > nothing with them. If you look in the dragonflybsd version of the > > driver it printed out all those values after reading them; whoever > > imported the driver to freebsd just deleted all the kprintf() lines and > > left the register reads. > > > > > -- > Gary Jennejohn >