From owner-freebsd-mobile Sun Oct 5 02:05:15 1997 Return-Path: Received: (from root@localhost) by hub.freebsd.org (8.8.7/8.8.7) id CAA08102 for mobile-outgoing; Sun, 5 Oct 1997 02:05:15 -0700 (PDT) Received: from Octopussy.MI.Uni-Koeln.DE (Octopussy.MI.Uni-Koeln.DE [134.95.166.20]) by hub.freebsd.org (8.8.7/8.8.7) with SMTP id CAA08096; Sun, 5 Oct 1997 02:05:09 -0700 (PDT) Received: from x14.mi.uni-koeln.de ([134.95.219.124]) by Octopussy.MI.Uni-Koeln.DE with SMTP id AA08037 (5.67b/IDA-1.5); Sun, 5 Oct 1997 11:05:06 +0200 Received: (from se@localhost) by x14.mi.uni-koeln.de (8.8.7/8.6.9) id JAA00365; Sun, 5 Oct 1997 09:35:05 +0200 (CEST) X-Face: " Date: Sun, 5 Oct 1997 09:35:05 +0200 From: Stefan Esser To: Satoshi Asami Cc: mobile@FreeBSD.ORG, Stefan Esser Subject: Re: chipset IDs for mobile PCs References: <199710010321.UAA01822@silvia.HIP.Berkeley.EDU> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Mailer: Mutt 0.84 In-Reply-To: <199710010321.UAA01822@silvia.HIP.Berkeley.EDU>; from Satoshi Asami on Tue, Sep 30, 1997 at 08:21:27PM -0700 Sender: owner-freebsd-mobile@FreeBSD.ORG X-Loop: FreeBSD.org Precedence: bulk On 1997-09-30 20:21 -0700, Satoshi Asami wrote: > The patch is relative to RELENG_2_2. I got the datasheets from > > http://developer.intel.com/design/pcisets/datashts/ > > ------- > Index: pcisupport.c > =================================================================== > RCS file: /usr/cvs/src/sys/pci/pcisupport.c,v > retrieving revision 1.40.2.4 > diff -u -r1.40.2.4 pcisupport.c > --- pcisupport.c 1997/07/18 19:48:22 1.40.2.4 > +++ pcisupport.c 1997/10/01 03:07:31 > @@ -136,6 +136,10 @@ > return ("Intel 82371FB PCI-ISA bridge"); > case 0x12308086: > return ("Intel 82371FB IDE interface"); > + case 0x12348086: > + return ("Intel 82371MX mobile PCI I/O IDE accelerator (MPIIX)"); > + case 0x12358086: > + return ("Intel 82437MX mobile PCI cache memory controller"); > case 0x12508086: > return ("Intel 82439"); > case 0x04061039: > ------- > > The 82371 is referred to as both "MX" and "MB" in their datasheets. I > went with the majority (for one, it is called "MX" in 82371's own > datasheet). The chip sets often contain parts that are connected to the PCI bus, and others that are not and can't decode PCI configuration cycles (e.g. buffer or driver chips). I didn't have time to check this on Intel's web site, for these particular devices, though. > Also, Intel's official name for the 82371MX is "Mobile PCI I/O IDE > Xcelerator (MPIIX)". I thought we can avoid that kind of ugliness. Well, it just seems to fit on one line in the boot message log. If Intel wants the chip to be known by that name ... > BTW, this is the output of boot -v after the patch. Thanks! Looks fine ... ** Could you please apply the patch to -current (and, if permitted ** by the release-engineer, to 2.2.5) ? This is one of the least dangerous patches I can imagine, and I think it should be allowed in ... Sorry, I'm overloaded at my job, currently, and did not have time to commit it before the code freeze. > pcibus_setup(1): mode 1 addr port (0x0cf8) is 0x80000050 > pcibus_setup(1a): mode1res=0x80000000 (0x80000000) > pcibus_check: device 0 is there (id=12358086) > Probing for devices on PCI bus 0: > configuration mode 1 allows 32 devices. > chip0 rev 2 on pci0:0 > chip1 rev 3 on pci0:1 > vga0 rev 211 int a irq ?? on pci0:3 > pcic0 rev 226 int a irq ?? on pci0:19 Regards, STefan