From owner-freebsd-mips@FreeBSD.ORG Sun Apr 7 02:57:07 2013 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.FreeBSD.org [8.8.178.115]) by hub.freebsd.org (Postfix) with ESMTP id 907F8CC7; Sun, 7 Apr 2013 02:57:07 +0000 (UTC) (envelope-from adrian.chadd@gmail.com) Received: from mail-wi0-x229.google.com (mail-wi0-x229.google.com [IPv6:2a00:1450:400c:c05::229]) by mx1.freebsd.org (Postfix) with ESMTP id 00D28EDD; Sun, 7 Apr 2013 02:57:06 +0000 (UTC) Received: by mail-wi0-f169.google.com with SMTP id c10so2882877wiw.0 for ; Sat, 06 Apr 2013 19:57:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=N1VmtVnD/whI0oyYLyMT1q+HSwnaBWs7nGVx8hW3CCU=; b=KRCn55vAUS7t9RTiSf04EPq0yVTf1hXS69PffYZe+nddCU6PndPrJH7VB7yO8Tzbp4 wzminnWkDzT0hwjnpTqx+Z0f4QxOWaKozFFhBSj0d/hgLPu6LebuY7Z7DlMf5tjklEOT 18sM1YZ4EgW45L9WtgxXp6YmM2pizywWUyFr01hVcssBB+pC+WObTJv5RaCDlmXv06ta U1azhh0Hync1MPcYuw0EZMwNqRnuXaLEzoV+bQ/3p38zkVB/zEdSHlmGkZY0eEj67iVq f7p1hUHrkf+go1BKsJACl865lQf3mT+Fqpo334d/GJL3egIS/xR3ABXzly+q7E7Oyjdo ZLXA== MIME-Version: 1.0 X-Received: by 10.194.143.50 with SMTP id sb18mr24548497wjb.44.1365303425801; Sat, 06 Apr 2013 19:57:05 -0700 (PDT) Sender: adrian.chadd@gmail.com Received: by 10.217.121.136 with HTTP; Sat, 6 Apr 2013 19:57:05 -0700 (PDT) In-Reply-To: <20130407022428.86a66c6a.ray@freebsd.org> References: <20130407011307.9a9a9d64.ray@freebsd.org> <20130407022428.86a66c6a.ray@freebsd.org> Date: Sat, 6 Apr 2013 19:57:05 -0700 X-Google-Sender-Auth: pR8l-masNElpvkyLbp6DDvGxqto Message-ID: Subject: Re: [PATCH] MMC/SD SPI-mode driver From: Adrian Chadd To: Aleksandr Rybalko Content-Type: text/plain; charset=ISO-8859-1 Cc: Dmytro , freebsd-mips@freebsd.org X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 07 Apr 2013 02:57:07 -0000 On 6 April 2013 16:24, Aleksandr Rybalko wrote: >> The other question is how we implement it. You've implemented a "get >> block" device method. That's a very atheros chipset specific hack just >> to get accelerated flash IO. Is there perhaps a better way to approach >> this? > > As I see, no way to put data back to flash. Well, look at the Linux code. If there's a read that can be satisfied by a copy, it: * puts the flash device back into mapped mode; * does the transfer; * puts the flash device back into SPI mode. That way both can occur independently. >> What about the 8 versus 32 bit shifting that I see in the driver? Are >> we able to actually shift 32 bits at a time? > > Currently we do 1 bit shifting :))) Pure, 1-bit control. > Maybe you (as Atheros guy) know how to shift more :))) Writes are clocked out like that, sure. But if I read the linux code right, they do up to 32 bits of shifting at once, then do a 32 bit read. Rather than us shifting a byte in/out at a time over SPI. Adrian