Date: Sun, 27 Jan 2013 16:06:22 GMT From: Robert Watson <rwatson@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 221534 for review Message-ID: <201301271606.r0RG6Ma7034449@skunkworks.freebsd.org>
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http://p4web.freebsd.org/@@221534?ac=10 Change 221534 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2013/01/27 16:05:30 FreeBSD/mips stores page-table entries in a near-identical format to MIPS TLB entries -- only it overrides certain "reserved" bits in the MIPS-defined EntryLo register to hold software-defined bits (swbits) to avoid significantly increasing the page table memory footprint. On n32 and n64, these bits were (a) colliding with MIPS64r2 physical memory extensions and (b) being improperly cleared. Attempt to fix both of these problems by pushing swbits further along 64-bit EntryLo registers into the reserved space, and improving consistency between C-based and assembly-based clearing of swbits -- in particular, to use the same definition. This should stop swbits from leaking into TLB entries -- while ignored by most current MIPS hardware, this would cause a problem with (much) larger physical memory sizes, and also leads to confusing hardware-level tracing as physical addresses contain unexpected (and inconsistent) higher bits. Discussed with: imp, jmallett Affected files ... .. //depot/projects/ctsrd/beribsd/src/sys/mips/include/pte.h#4 edit Differences ... ==== //depot/projects/ctsrd/beribsd/src/sys/mips/include/pte.h#4 (text+ko) ==== @@ -56,16 +56,26 @@ #define TLBMASK_MASK ((PAGE_MASK >> TLBMASK_SHIFT) << TLBMASK_SHIFT) /* - * PFN for EntryLo register. Upper bits are 0, which is to say that - * bit 28 is the last hardware bit; Bits 29 and upwards (EntryLo is - * 64 bit though it can be referred to in 32-bits providing 3 software - * bits safely. We use it as 64 bits to get many software bits, and - * god knows what else.) are unacknowledged by hardware. They may be - * written as anything, but otherwise they have as much meaning as - * other 0 fields. + * FreeBSD/mips page-table entries take a near-identical format to MIPS TLB + * entries, each consisting of two 32-bit or 64-bit values ("EntryHi" and + * "EntryLo"). MIPS4k and MIPS64 both define certain bits in TLB entries as + * reserved, and these must be zero-filled by software. We overload these + * bits in PTE entries to hold PTE_ flags such as RO, W, and MANAGED. + * However, we must mask these out when writing to TLB entries to ensure that + * they do not become visible to hardware -- especially on MIPS64r2 which has + * an extended physical memory space. + * + * When using n64 and n32, shift software-defined bits into the MIPS64r2 + * reserved range, which runs from bit 55 ... 63. In other configurations + * (32-bit MIPS4k and compatible), shift them out to bits 29 ... 31. + * + * NOTE: This means that for 32-bit use of CP0, we aren't able to set the top + * bit of PFN to a non-zero value, as software is using it! This physical + * memory size limit may not be sufficiently enforced elsewhere. */ #if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */ -#define TLBLO_SWBITS_SHIFT (34) +#define TLBLO_SWBITS_SHIFT (55) +#define TLBLO_SWBITS_CLEAR_SHIFT (9) #define TLBLO_PFN_MASK 0x3FFFFFFC0ULL #else #define TLBLO_SWBITS_SHIFT (29) @@ -133,6 +143,9 @@ * listen to requests to write to it. * W: Wired. ??? * MANAGED:Managed. This PTE maps a managed page. + * + * These bits should not be written into the TLB, so must first be masked out + * explicitly in C, or using CLEAR_PTE_SWBITS() in assembly. */ #define PTE_RO ((pt_entry_t)0x01 << TLBLO_SWBITS_SHIFT) #define PTE_W ((pt_entry_t)0x02 << TLBLO_SWBITS_SHIFT) @@ -162,7 +175,7 @@ #define PTESIZE 4 #define PTE_L lw #define PTE_MTC0 mtc0 -#define CLEAR_PTE_SWBITS(r) sll r, 3; srl r, 3 /* remove 3 high bits */ +#define CLEAR_PTE_SWBITS(r) LONG_SLL r, TLBLO_SWBITS_CLEAR_SHIFT; LONG_SRL r, TLBLO_SWBITS_CLEAR_SHIFT /* remove swbits */ #endif /* defined(__mips_n64) || defined(__mips_n32) */ #if defined(__mips_n64)
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