Date: Mon, 8 Apr 2013 16:22:49 GMT From: David Chisnall <theraven@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 227508 for review Message-ID: <201304081622.r38GMnv5090769@skunkworks.freebsd.org>
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http://p4web.freebsd.org/@@227508?ac=10 Change 227508 by theraven@theraven_zenith_mipsbuild on 2013/04/08 16:21:49 Initial pass at letting the kernel debugger understand CHERI instructions. Please test! Affected files ... .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/mips_opcode.h#3 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/db_disasm.c#3 edit Differences ... ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/mips_opcode.h#3 (text+ko) ==== @@ -82,6 +82,43 @@ unsigned fd: 5; unsigned func: 6; } FRType; + +#ifdef CPU_CHERI + /* Capability memory operations */ + struct { + unsigned op: 6; + unsigned rd: 5; + unsigned cb: 5; + unsigned rt: 5; + unsigned offset: 8; + unsigned fmt: 3; + } CMType; + /* Capability atomic memory operations */ + struct { + unsigned op: 6; + unsigned cs: 5; + unsigned cb: 5; + unsigned rt: 5; + int offset: 10; + } CCMType; + /* Most other capability instructions */ + struct { + unsigned op: 6; + unsigned fmt: 5; + unsigned r1: 5; + unsigned r2: 5; + unsigned r3: 5; + unsigned unused: 3; + unsigned fmt2: 3; + } CType; + /* BC2F format */ + struct { + unsigned op: 6; + unsigned fmt: 5; + unsigned cd: 5; + unsigned offset: 16; + } BC2FType; +#endif /* CPU_CHERI */ #endif #if BYTE_ORDER == LITTLE_ENDIAN struct { ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/db_disasm.c#3 (text+ko) ==== @@ -127,6 +127,37 @@ "c0r24","c0r25","ecc","cacheerr","taglo","taghi","errepc","c0r31" }; +#ifdef CPU_CHERI +static const char *cheri_cap_load_opname[8] = { + "clbu", "clhu", "clwu", "cldu", + "clb", "clh", "clw", "clld" +}; +static const char *cheri_cap_store_opname[8] = { + "csb", "csh", "csw", "csd", + "csb", "csh", "csw", "cscd" +}; +static const char *cheri_flow_control_opname[16] = { + "invalid", "CSealCode", "CSealData", "CUnseal", + "invalid", "CCall", "CReturn", "cjalr", + "cjr", "invalid", "invalid", "invalid", + "invalid", "invalid", "invalid", "invalid" +}; +static const char *cheri_cap_inspect_opname[8] = { + "CGetPerm", "CGetType", "CGetBase", "CGetLen", + "invalid", "CGetTag", "CGetUnsealed", "CGetPCC" +}; +static const char *cheri_cap_modify_name[8] = { + "CAndPerm", "CSetType", "CIncBase", "CSetLen", + "invalid", "CClearTag", "invalid", "invalid" +}; +static const char *c2_reg[32] = { + "c0", "c1", "c2", "c3", "c4", "c5", "c6", "c7", "c8", "c9", + "c10", "c11", "c12", "c13", "c14", "c15", "c16", "c17", "c18", "c19", + "c20", "c21", "c22", "c23", "c24", "c25", "idc", "kr2c", "kr2c", "kcc", + "kdc", "epcc" +}; +#endif /* CPU_CHERI */ + static int md_printins(int ins, int mdbdot); db_addr_t @@ -258,6 +289,84 @@ db_printf("0x%08x", mdbdot + 4 + ((short)i.IType.imm << 2)); break; +#ifdef CPU_CHERI + case OP_COP2: { + unsigned ops = 0; + const char *opcode = "invalid"; + const char *operands[3] = { 0 }; + switch (i.CType.fmt) { + case 0: + ops = 2; + opcode = cheri_cap_inspect_opname[i.CType.fmt2]; + operands[0] = reg_name[i.CType.r1]; + operands[1] = c2_reg[i.CType.r2]; + break; + case 4: + ops = i.CType.fmt2 == 5 ? 0 : 3; + opcode = cheri_cap_modify_name[i.CType.fmt2]; + operands[0] = reg_name[i.CType.r1]; + operands[1] = c2_reg[i.CType.r2]; + break; + case 1: + case 5: + ops = 2; + opcode = cheri_flow_control_opname[i.CType.fmt]; + operands[0] = c2_reg[i.CType.r1]; + operands[1] = c2_reg[i.CType.r2]; + break; + case 2: + case 3: + ops = 3; + opcode = cheri_flow_control_opname[i.CType.fmt]; + operands[0] = c2_reg[i.CType.r1]; + operands[1] = c2_reg[i.CType.r2]; + operands[2] = c2_reg[i.CType.r3]; + break; + case 7: + case 8: + ops = 2; + opcode = cheri_flow_control_opname[i.CType.fmt]; + operands[0] = c2_reg[i.CType.r2]; + operands[1] = reg_name[i.CType.r3]; + break; + case 6: + opcode = cheri_flow_control_opname[i.CType.fmt]; + } + + switch (ops) { + case 0: + db_printf("%s\n", opcode); + break; + case 1: + db_printf("%s\t%s\n", opcode, operands[0]); + break; + case 2: + db_printf("%s\t%s,%s\n", opcode, operands[0], operands[1]); + break; + case 3: + db_printf("%s\t%s,%s,%s\n", opcode, operands[0], operands[1], + operands[2]); + } + } + break; + case OP_LWC2: + case OP_SWC2: { + const char *opcode = i.JType.op == OP_LWC2 ? + cheri_cap_load_opname[i.CMType.fmt] : + cheri_cap_store_opname[i.CMType.fmt]; + db_printf("%s\t%s, %s, %d(%s)\n", opcode, reg_name[i.CType.r1], + reg_name[i.CType.r3], i.CMType.offset, c2_reg[i.CType.r2]); + break; + } + case OP_LDC2: + case OP_SDC2: { + const char *opcode = i.JType.op == OP_LDC2 ? "clc" : "csc"; + db_printf("%s\t%s, %s, %d(%s)\n", opcode, c2_reg[i.CType.r1], + reg_name[i.CType.r3], i.CMType.offset, c2_reg[i.CType.r2]); + break; + } +#endif /* CPU_CHERI */ + case OP_COP0: switch (i.RType.rs) { case OP_BCx:
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