From owner-svn-src-vendor@freebsd.org Wed Jun 27 19:14:22 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 380941002EF7; Wed, 27 Jun 2018 19:14:22 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id BC1F98D9CE; Wed, 27 Jun 2018 19:14:21 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 84250272FA; Wed, 27 Jun 2018 19:14:21 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5RJEL7E042870; Wed, 27 Jun 2018 19:14:21 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5RJELpe042869; Wed, 27 Jun 2018 19:14:21 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201806271914.w5RJELpe042869@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 27 Jun 2018 19:14:21 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335721 - vendor/llvm/llvm-release_601-r335540 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/llvm/llvm-release_601-r335540 X-SVN-Commit-Revision: 335721 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jun 2018 19:14:22 -0000 Author: dim Date: Wed Jun 27 19:14:21 2018 New Revision: 335721 URL: https://svnweb.freebsd.org/changeset/base/335721 Log: Tag llvm 6.0.1 release r335540. Added: vendor/llvm/llvm-release_601-r335540/ - copied from r335720, vendor/llvm/dist-release_60/ From owner-svn-src-vendor@freebsd.org Wed Jun 27 19:14:19 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 91CBA1002EF1; Wed, 27 Jun 2018 19:14:18 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 407EA8D9C0; Wed, 27 Jun 2018 19:14:18 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 1E98D272F9; Wed, 27 Jun 2018 19:14:18 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5RJEH9K042824; Wed, 27 Jun 2018 19:14:17 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5RJE94Y042787; Wed, 27 Jun 2018 19:14:09 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201806271914.w5RJE94Y042787@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 27 Jun 2018 19:14:09 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335720 - in vendor/llvm/dist-release_60: . include/llvm/CodeGen include/llvm/IR lib/Analysis lib/CodeGen lib/ExecutionEngine/RuntimeDyld lib/IR lib/MC lib/Support lib/Target/AArch64 li... X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in vendor/llvm/dist-release_60: . include/llvm/CodeGen include/llvm/IR lib/Analysis lib/CodeGen lib/ExecutionEngine/RuntimeDyld lib/IR lib/MC lib/Support lib/Target/AArch64 lib/Target/AMDGPU lib/Targe... X-SVN-Commit-Revision: 335720 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jun 2018 19:14:19 -0000 Author: dim Date: Wed Jun 27 19:14:09 2018 New Revision: 335720 URL: https://svnweb.freebsd.org/changeset/base/335720 Log: Vendor import of llvm 6.0.1 release r335540: https://llvm.org/svn/llvm-project/llvm/tags/RELEASE_601/final@335540 Added: vendor/llvm/dist-release_60/lib/Target/X86/X86FlagsCopyLowering.cpp (contents, props changed) vendor/llvm/dist-release_60/test/Analysis/MemorySSA/pr36883.ll vendor/llvm/dist-release_60/test/CodeGen/AArch64/inlineasm-S-constraint.ll vendor/llvm/dist-release_60/test/CodeGen/AArch64/spill-stack-realignment.mir vendor/llvm/dist-release_60/test/CodeGen/AMDGPU/ctpop16.ll vendor/llvm/dist-release_60/test/CodeGen/Hexagon/ifcvt-diamond-ret.mir vendor/llvm/dist-release_60/test/CodeGen/MIR/PowerPC/ifcvt-diamond-ret.mir vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/ vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/calls.ll vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/long-branch.ll vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/long-calls.ll vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/unsupported-micromips.ll vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/unsupported-mips32.ll vendor/llvm/dist-release_60/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l1.ll vendor/llvm/dist-release_60/test/CodeGen/PowerPC/no-dup-of-bdnz.ll vendor/llvm/dist-release_60/test/CodeGen/PowerPC/pr35402.ll vendor/llvm/dist-release_60/test/CodeGen/Thumb/PR36658.mir vendor/llvm/dist-release_60/test/CodeGen/X86/domain-reassignment-implicit-def.ll vendor/llvm/dist-release_60/test/CodeGen/X86/domain-reassignment-test.ll vendor/llvm/dist-release_60/test/CodeGen/X86/flags-copy-lowering.mir vendor/llvm/dist-release_60/test/CodeGen/X86/pr37264.ll vendor/llvm/dist-release_60/test/DebugInfo/X86/live-debug-vars-discard-invalid.mir vendor/llvm/dist-release_60/test/ExecutionEngine/RuntimeDyld/PowerPC/Inputs/ vendor/llvm/dist-release_60/test/ExecutionEngine/RuntimeDyld/PowerPC/Inputs/ppc64_elf_module_b.s (contents, props changed) vendor/llvm/dist-release_60/test/ExecutionEngine/RuntimeDyld/PowerPC/ppc64_elf.s (contents, props changed) vendor/llvm/dist-release_60/test/MC/Mips/unsupported-relocation.s (contents, props changed) vendor/llvm/dist-release_60/test/Transforms/ArgumentPromotion/musttail.ll vendor/llvm/dist-release_60/test/Transforms/CallSiteSplitting/musttail.ll vendor/llvm/dist-release_60/test/Transforms/DeadArgElim/musttail-caller.ll vendor/llvm/dist-release_60/test/Transforms/GlobalOpt/musttail_cc.ll vendor/llvm/dist-release_60/test/Transforms/IPConstantProp/musttail-call.ll vendor/llvm/dist-release_60/test/Transforms/JumpThreading/header-succ.ll vendor/llvm/dist-release_60/test/Transforms/MergeFunc/inline-asm.ll vendor/llvm/dist-release_60/test/Transforms/MergeFunc/weak-small.ll Deleted: vendor/llvm/dist-release_60/test/CodeGen/X86/clobber-fi0.ll vendor/llvm/dist-release_60/test/CodeGen/X86/eflags-copy-expansion.mir Modified: vendor/llvm/dist-release_60/CMakeLists.txt vendor/llvm/dist-release_60/include/llvm/CodeGen/MachineBasicBlock.h vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetInstrInfo.h vendor/llvm/dist-release_60/include/llvm/IR/IntrinsicsPowerPC.td vendor/llvm/dist-release_60/lib/Analysis/GlobalsModRef.cpp vendor/llvm/dist-release_60/lib/Analysis/MemorySSA.cpp vendor/llvm/dist-release_60/lib/CodeGen/IfConversion.cpp vendor/llvm/dist-release_60/lib/CodeGen/LiveDebugVariables.cpp vendor/llvm/dist-release_60/lib/CodeGen/MachineBasicBlock.cpp vendor/llvm/dist-release_60/lib/CodeGen/MachineBlockPlacement.cpp vendor/llvm/dist-release_60/lib/CodeGen/PeepholeOptimizer.cpp vendor/llvm/dist-release_60/lib/CodeGen/TargetInstrInfo.cpp vendor/llvm/dist-release_60/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp vendor/llvm/dist-release_60/lib/IR/Core.cpp vendor/llvm/dist-release_60/lib/MC/MCObjectFileInfo.cpp vendor/llvm/dist-release_60/lib/Support/CMakeLists.txt vendor/llvm/dist-release_60/lib/Support/Host.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64AsmPrinter.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FrameLowering.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64ISelLowering.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstrInfo.td vendor/llvm/dist-release_60/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIISelLowering.cpp vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInstructions.td vendor/llvm/dist-release_60/lib/Target/ARM/ARMBaseInstrInfo.cpp vendor/llvm/dist-release_60/lib/Target/ARM/ARMComputeBlockSize.cpp vendor/llvm/dist-release_60/lib/Target/Mips/AsmParser/MipsAsmParser.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MicroMips32r6InstrInfo.td vendor/llvm/dist-release_60/lib/Target/Mips/MicroMipsInstrInfo.td vendor/llvm/dist-release_60/lib/Target/Mips/Mips.td vendor/llvm/dist-release_60/lib/Target/Mips/Mips32r6InstrInfo.td vendor/llvm/dist-release_60/lib/Target/Mips/Mips64InstrInfo.td vendor/llvm/dist-release_60/lib/Target/Mips/Mips64r6InstrInfo.td vendor/llvm/dist-release_60/lib/Target/Mips/MipsDSPInstrFormats.td vendor/llvm/dist-release_60/lib/Target/Mips/MipsFastISel.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MipsISelLowering.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MipsInstrFormats.td vendor/llvm/dist-release_60/lib/Target/Mips/MipsInstrInfo.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MipsInstrInfo.td vendor/llvm/dist-release_60/lib/Target/Mips/MipsLongBranch.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MipsSEISelLowering.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MipsSubtarget.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MipsSubtarget.h vendor/llvm/dist-release_60/lib/Target/NVPTX/NVPTXTargetMachine.cpp vendor/llvm/dist-release_60/lib/Target/PowerPC/PPCISelLowering.cpp vendor/llvm/dist-release_60/lib/Target/PowerPC/PPCInstrInfo.cpp vendor/llvm/dist-release_60/lib/Target/X86/CMakeLists.txt vendor/llvm/dist-release_60/lib/Target/X86/Disassembler/X86Disassembler.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86.h vendor/llvm/dist-release_60/lib/Target/X86/X86DomainReassignment.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86FastISel.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.h vendor/llvm/dist-release_60/lib/Target/X86/X86InstrArithmetic.td vendor/llvm/dist-release_60/lib/Target/X86/X86InstrCompiler.td vendor/llvm/dist-release_60/lib/Target/X86/X86InstrInfo.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86InstrInfo.h vendor/llvm/dist-release_60/lib/Target/X86/X86InstrInfo.td vendor/llvm/dist-release_60/lib/Target/X86/X86InstrSystem.td vendor/llvm/dist-release_60/lib/Target/X86/X86RegisterInfo.td vendor/llvm/dist-release_60/lib/Target/X86/X86Schedule.td vendor/llvm/dist-release_60/lib/Target/X86/X86ScheduleAtom.td vendor/llvm/dist-release_60/lib/Target/X86/X86TargetMachine.cpp vendor/llvm/dist-release_60/lib/Transforms/IPO/ArgumentPromotion.cpp vendor/llvm/dist-release_60/lib/Transforms/IPO/DeadArgumentElimination.cpp vendor/llvm/dist-release_60/lib/Transforms/IPO/GlobalOpt.cpp vendor/llvm/dist-release_60/lib/Transforms/IPO/MergeFunctions.cpp vendor/llvm/dist-release_60/lib/Transforms/InstCombine/InstructionCombining.cpp vendor/llvm/dist-release_60/lib/Transforms/Scalar/CallSiteSplitting.cpp vendor/llvm/dist-release_60/lib/Transforms/Scalar/DivRemPairs.cpp vendor/llvm/dist-release_60/lib/Transforms/Scalar/JumpThreading.cpp vendor/llvm/dist-release_60/lib/Transforms/Scalar/SCCP.cpp vendor/llvm/dist-release_60/lib/Transforms/Utils/FunctionComparator.cpp vendor/llvm/dist-release_60/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll vendor/llvm/dist-release_60/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll vendor/llvm/dist-release_60/test/CodeGen/AArch64/falkor-hwpf-fix.mir vendor/llvm/dist-release_60/test/CodeGen/ARM/peephole-phi.mir vendor/llvm/dist-release_60/test/CodeGen/Mips/const-mult.ll vendor/llvm/dist-release_60/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll vendor/llvm/dist-release_60/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir vendor/llvm/dist-release_60/test/CodeGen/X86/GlobalISel/add-scalar.ll vendor/llvm/dist-release_60/test/CodeGen/X86/O0-pipeline.ll vendor/llvm/dist-release_60/test/CodeGen/X86/cmpxchg-clobber-flags.ll vendor/llvm/dist-release_60/test/CodeGen/X86/copy-eflags.ll vendor/llvm/dist-release_60/test/CodeGen/X86/fast-isel-shift.ll vendor/llvm/dist-release_60/test/CodeGen/X86/ipra-reg-usage.ll vendor/llvm/dist-release_60/test/CodeGen/X86/mul-i1024.ll vendor/llvm/dist-release_60/test/CodeGen/X86/peephole-na-phys-copy-folding.ll vendor/llvm/dist-release_60/test/CodeGen/X86/win64_frame.ll vendor/llvm/dist-release_60/test/CodeGen/X86/x86-repmov-copy-eflags.ll vendor/llvm/dist-release_60/test/DebugInfo/X86/dbg-value-inlined-parameter.ll vendor/llvm/dist-release_60/test/MC/ELF/cfi-large-model.s vendor/llvm/dist-release_60/test/Transforms/InstCombine/gep-addrspace.ll vendor/llvm/dist-release_60/tools/llvm-config/CMakeLists.txt Modified: vendor/llvm/dist-release_60/CMakeLists.txt ============================================================================== --- vendor/llvm/dist-release_60/CMakeLists.txt Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/CMakeLists.txt Wed Jun 27 19:14:09 2018 (r335720) @@ -24,7 +24,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR) set(LLVM_VERSION_MINOR 0) endif() if(NOT DEFINED LLVM_VERSION_PATCH) - set(LLVM_VERSION_PATCH 0) + set(LLVM_VERSION_PATCH 1) endif() if(NOT DEFINED LLVM_VERSION_SUFFIX) set(LLVM_VERSION_SUFFIX "") Modified: vendor/llvm/dist-release_60/include/llvm/CodeGen/MachineBasicBlock.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/CodeGen/MachineBasicBlock.h Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/include/llvm/CodeGen/MachineBasicBlock.h Wed Jun 27 19:14:09 2018 (r335720) @@ -449,6 +449,13 @@ class MachineBasicBlock (public) /// Replace successor OLD with NEW and update probability info. void replaceSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New); + /// Copy a successor (and any probability info) from original block to this + /// block's. Uses an iterator into the original blocks successors. + /// + /// This is useful when doing a partial clone of successors. Afterward, the + /// probabilities may need to be normalized. + void copySuccessor(MachineBasicBlock *Orig, succ_iterator I); + /// Transfers all the successors from MBB to this machine basic block (i.e., /// copies all the successors FromMBB and remove all the successors from /// FromMBB). Modified: vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetInstrInfo.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetInstrInfo.h Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetInstrInfo.h Wed Jun 27 19:14:09 2018 (r335720) @@ -421,7 +421,8 @@ class TargetInstrInfo : public MCInstrInfo { (public) /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI /// and \p DefIdx. /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of - /// the list is modeled as . + /// the list is modeled as . Operands with the undef + /// flag are not added to this list. /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce /// two elements: /// - %1:sub1, sub0 @@ -446,7 +447,8 @@ class TargetInstrInfo : public MCInstrInfo { (public) /// - %1:sub1, sub0 /// /// \returns true if it is possible to build such an input sequence - /// with the pair \p MI, \p DefIdx. False otherwise. + /// with the pair \p MI, \p DefIdx and the operand has no undef flag set. + /// False otherwise. /// /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike(). /// @@ -465,7 +467,8 @@ class TargetInstrInfo : public MCInstrInfo { (public) /// - InsertedReg: %1:sub1, sub3 /// /// \returns true if it is possible to build such an input sequence - /// with the pair \p MI, \p DefIdx. False otherwise. + /// with the pair \p MI, \p DefIdx and the operand has no undef flag set. + /// False otherwise. /// /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike(). /// Modified: vendor/llvm/dist-release_60/include/llvm/IR/IntrinsicsPowerPC.td ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/IR/IntrinsicsPowerPC.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/include/llvm/IR/IntrinsicsPowerPC.td Wed Jun 27 19:14:09 2018 (r335720) @@ -36,8 +36,12 @@ let TargetPrefix = "ppc" in { // All intrinsics start // Intrinsics used to generate ctr-based loops. These should only be // generated by the PowerPC backend! + // The branch intrinsic is marked as NoDuplicate because loop rotation will + // attempt to duplicate it forming loops where a block reachable from one + // instance of it can contain another. def int_ppc_mtctr : Intrinsic<[], [llvm_anyint_ty], []>; - def int_ppc_is_decremented_ctr_nonzero : Intrinsic<[llvm_i1_ty], [], []>; + def int_ppc_is_decremented_ctr_nonzero : + Intrinsic<[llvm_i1_ty], [], [IntrNoDuplicate]>; // Intrinsics for [double]word extended forms of divide instructions def int_ppc_divwe : GCCBuiltin<"__builtin_divwe">, Modified: vendor/llvm/dist-release_60/lib/Analysis/GlobalsModRef.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Analysis/GlobalsModRef.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Analysis/GlobalsModRef.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -502,6 +502,8 @@ void GlobalsAAResult::AnalyzeCallGraph(CallGraph &CG, } FunctionInfo &FI = FunctionInfos[F]; + Handles.emplace_front(*this, F); + Handles.front().I = Handles.begin(); bool KnowNothing = false; // Collect the mod/ref properties due to called functions. We only compute Modified: vendor/llvm/dist-release_60/lib/Analysis/MemorySSA.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Analysis/MemorySSA.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Analysis/MemorySSA.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -153,9 +153,14 @@ class MemoryLocOrCall { (public) if (IsCall != Other.IsCall) return false; - if (IsCall) - return CS.getCalledValue() == Other.CS.getCalledValue(); - return Loc == Other.Loc; + if (!IsCall) + return Loc == Other.Loc; + + if (CS.getCalledValue() != Other.CS.getCalledValue()) + return false; + + return CS.arg_size() == Other.CS.arg_size() && + std::equal(CS.arg_begin(), CS.arg_end(), Other.CS.arg_begin()); } private: @@ -179,12 +184,18 @@ template <> struct DenseMapInfo { } static unsigned getHashValue(const MemoryLocOrCall &MLOC) { - if (MLOC.IsCall) - return hash_combine(MLOC.IsCall, - DenseMapInfo::getHashValue( - MLOC.getCS().getCalledValue())); - return hash_combine( - MLOC.IsCall, DenseMapInfo::getHashValue(MLOC.getLoc())); + if (!MLOC.IsCall) + return hash_combine( + MLOC.IsCall, + DenseMapInfo::getHashValue(MLOC.getLoc())); + + hash_code hash = + hash_combine(MLOC.IsCall, DenseMapInfo::getHashValue( + MLOC.getCS().getCalledValue())); + + for (const Value *Arg : MLOC.getCS().args()) + hash = hash_combine(hash, DenseMapInfo::getHashValue(Arg)); + return hash; } static bool isEqual(const MemoryLocOrCall &LHS, const MemoryLocOrCall &RHS) { Modified: vendor/llvm/dist-release_60/lib/CodeGen/IfConversion.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/IfConversion.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/CodeGen/IfConversion.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -1714,20 +1714,25 @@ bool IfConverter::IfConvertDiamondCommon( } // Remove the duplicated instructions at the beginnings of both paths. - // Skip dbg_value instructions + // Skip dbg_value instructions. MachineBasicBlock::iterator DI1 = MBB1.getFirstNonDebugInstr(); MachineBasicBlock::iterator DI2 = MBB2.getFirstNonDebugInstr(); BBI1->NonPredSize -= NumDups1; BBI2->NonPredSize -= NumDups1; // Skip past the dups on each side separately since there may be - // differing dbg_value entries. + // differing dbg_value entries. NumDups1 can include a "return" + // instruction, if it's not marked as "branch". for (unsigned i = 0; i < NumDups1; ++DI1) { + if (DI1 == MBB1.end()) + break; if (!DI1->isDebugValue()) ++i; } while (NumDups1 != 0) { ++DI2; + if (DI2 == MBB2.end()) + break; if (!DI2->isDebugValue()) --NumDups1; } @@ -1738,11 +1743,16 @@ bool IfConverter::IfConvertDiamondCommon( Redefs.stepForward(MI, Dummy); } } + BBI.BB->splice(BBI.BB->end(), &MBB1, MBB1.begin(), DI1); MBB2.erase(MBB2.begin(), DI2); - // The branches have been checked to match, so it is safe to remove the branch - // in BB1 and rely on the copy in BB2 + // The branches have been checked to match, so it is safe to remove the + // branch in BB1 and rely on the copy in BB2. The complication is that + // the blocks may end with a return instruction, which may or may not + // be marked as "branch". If it's not, then it could be included in + // "dups1", leaving the blocks potentially empty after moving the common + // duplicates. #ifndef NDEBUG // Unanalyzable branches must match exactly. Check that now. if (!BBI1->IsBrAnalyzable) @@ -1768,11 +1778,14 @@ bool IfConverter::IfConvertDiamondCommon( if (RemoveBranch) BBI2->NonPredSize -= TII->removeBranch(*BBI2->BB); else { - do { - assert(DI2 != MBB2.begin()); - DI2--; - } while (DI2->isBranch() || DI2->isDebugValue()); - DI2++; + // Make DI2 point to the end of the range where the common "tail" + // instructions could be found. + while (DI2 != MBB2.begin()) { + MachineBasicBlock::iterator Prev = std::prev(DI2); + if (!Prev->isBranch() && !Prev->isDebugValue()) + break; + DI2 = Prev; + } } while (NumDups2 != 0) { // NumDups2 only counted non-dbg_value instructions, so this won't @@ -1833,11 +1846,15 @@ bool IfConverter::IfConvertDiamondCommon( // a non-predicated in BBI2, then we don't want to predicate the one from // BBI2. The reason is that if we merged these blocks, we would end up with // two predicated terminators in the same block. + // Also, if the branches in MBB1 and MBB2 were non-analyzable, then don't + // predicate them either. They were checked to be identical, and so the + // same branch would happen regardless of which path was taken. if (!MBB2.empty() && (DI2 == MBB2.end())) { MachineBasicBlock::iterator BBI1T = MBB1.getFirstTerminator(); MachineBasicBlock::iterator BBI2T = MBB2.getFirstTerminator(); - if (BBI1T != MBB1.end() && TII->isPredicated(*BBI1T) && - BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T)) + bool BB1Predicated = BBI1T != MBB1.end() && TII->isPredicated(*BBI1T); + bool BB2NonPredicated = BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T); + if (BB2NonPredicated && (BB1Predicated || !BBI2->IsBrAnalyzable)) --DI2; } Modified: vendor/llvm/dist-release_60/lib/CodeGen/LiveDebugVariables.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/LiveDebugVariables.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/CodeGen/LiveDebugVariables.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -514,6 +514,39 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotI return false; } + // Detect invalid DBG_VALUE instructions, with a debug-use of a virtual + // register that hasn't been defined yet. If we do not remove those here, then + // the re-insertion of the DBG_VALUE instruction after register allocation + // will be incorrect. + // TODO: If earlier passes are corrected to generate sane debug information + // (and if the machine verifier is improved to catch this), then these checks + // could be removed or replaced by asserts. + bool Discard = false; + if (MI.getOperand(0).isReg() && + TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg())) { + const unsigned Reg = MI.getOperand(0).getReg(); + if (!LIS->hasInterval(Reg)) { + // The DBG_VALUE is described by a virtual register that does not have a + // live interval. Discard the DBG_VALUE. + Discard = true; + DEBUG(dbgs() << "Discarding debug info (no LIS interval): " + << Idx << " " << MI); + } else { + // The DBG_VALUE is only valid if either Reg is live out from Idx, or Reg + // is defined dead at Idx (where Idx is the slot index for the instruction + // preceeding the DBG_VALUE). + const LiveInterval &LI = LIS->getInterval(Reg); + LiveQueryResult LRQ = LI.Query(Idx); + if (!LRQ.valueOutOrDead()) { + // We have found a DBG_VALUE with the value in a virtual register that + // is not live. Discard the DBG_VALUE. + Discard = true; + DEBUG(dbgs() << "Discarding debug info (reg not live): " + << Idx << " " << MI); + } + } + } + // Get or create the UserValue for (variable,offset) here. bool IsIndirect = MI.getOperand(1).isImm(); if (IsIndirect) @@ -522,7 +555,13 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotI const DIExpression *Expr = MI.getDebugExpression(); UserValue *UV = getUserValue(Var, Expr, MI.getDebugLoc()); - UV->addDef(Idx, MI.getOperand(0), IsIndirect); + if (!Discard) + UV->addDef(Idx, MI.getOperand(0), IsIndirect); + else { + MachineOperand MO = MachineOperand::CreateReg(0U, false); + MO.setIsDebug(); + UV->addDef(Idx, MO, false); + } return true; } Modified: vendor/llvm/dist-release_60/lib/CodeGen/MachineBasicBlock.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/MachineBasicBlock.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/CodeGen/MachineBasicBlock.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -646,6 +646,14 @@ void MachineBasicBlock::replaceSuccessor(MachineBasicB removeSuccessor(OldI); } +void MachineBasicBlock::copySuccessor(MachineBasicBlock *Orig, + succ_iterator I) { + if (Orig->Probs.empty()) + addSuccessor(*I, Orig->getSuccProbability(I)); + else + addSuccessorWithoutProb(*I); +} + void MachineBasicBlock::addPredecessor(MachineBasicBlock *Pred) { Predecessors.push_back(Pred); } Modified: vendor/llvm/dist-release_60/lib/CodeGen/MachineBlockPlacement.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/MachineBlockPlacement.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/CodeGen/MachineBlockPlacement.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -513,6 +513,11 @@ class MachineBlockPlacement : public MachineFunctionPa bool runOnMachineFunction(MachineFunction &F) override; + bool allowTailDupPlacement() const { + assert(F); + return TailDupPlacement && !F->getTarget().requiresStructuredCFG(); + } + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired(); AU.addRequired(); @@ -1018,7 +1023,7 @@ MachineBlockPlacement::getBestTrellisSuccessor( MachineBasicBlock *Succ1 = BestA.Dest; MachineBasicBlock *Succ2 = BestB.Dest; // Check to see if tail-duplication would be profitable. - if (TailDupPlacement && shouldTailDuplicate(Succ2) && + if (allowTailDupPlacement() && shouldTailDuplicate(Succ2) && canTailDuplicateUnplacedPreds(BB, Succ2, Chain, BlockFilter) && isProfitableToTailDup(BB, Succ2, MBPI->getEdgeProbability(BB, Succ1), Chain, BlockFilter)) { @@ -1044,7 +1049,7 @@ MachineBlockPlacement::getBestTrellisSuccessor( return Result; } -/// When the option TailDupPlacement is on, this method checks if the +/// When the option allowTailDupPlacement() is on, this method checks if the /// fallthrough candidate block \p Succ (of block \p BB) can be tail-duplicated /// into all of its unplaced, unfiltered predecessors, that are not BB. bool MachineBlockPlacement::canTailDuplicateUnplacedPreds( @@ -1493,7 +1498,7 @@ MachineBlockPlacement::selectBestSuccessor( if (hasBetterLayoutPredecessor(BB, Succ, SuccChain, SuccProb, RealSuccProb, Chain, BlockFilter)) { // If tail duplication would make Succ profitable, place it. - if (TailDupPlacement && shouldTailDuplicate(Succ)) + if (allowTailDupPlacement() && shouldTailDuplicate(Succ)) DupCandidates.push_back(std::make_tuple(SuccProb, Succ)); continue; } @@ -1702,7 +1707,7 @@ void MachineBlockPlacement::buildChain( auto Result = selectBestSuccessor(BB, Chain, BlockFilter); MachineBasicBlock* BestSucc = Result.BB; bool ShouldTailDup = Result.ShouldTailDup; - if (TailDupPlacement) + if (allowTailDupPlacement()) ShouldTailDup |= (BestSucc && shouldTailDuplicate(BestSucc)); // If an immediate successor isn't available, look for the best viable @@ -1724,7 +1729,7 @@ void MachineBlockPlacement::buildChain( // Placement may have changed tail duplication opportunities. // Check for that now. - if (TailDupPlacement && BestSucc && ShouldTailDup) { + if (allowTailDupPlacement() && BestSucc && ShouldTailDup) { // If the chosen successor was duplicated into all its predecessors, // don't bother laying it out, just go round the loop again with BB as // the chain end. @@ -2758,7 +2763,7 @@ bool MachineBlockPlacement::runOnMachineFunction(Machi TailDupSize = TailDupPlacementAggressiveThreshold; } - if (TailDupPlacement) { + if (allowTailDupPlacement()) { MPDT = &getAnalysis(); if (MF.getFunction().optForSize()) TailDupSize = 1; Modified: vendor/llvm/dist-release_60/lib/CodeGen/PeepholeOptimizer.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/PeepholeOptimizer.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/CodeGen/PeepholeOptimizer.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -1882,6 +1882,8 @@ ValueTrackerResult ValueTracker::getNextSourceFromCopy return ValueTrackerResult(); // Otherwise, we want the whole source. const MachineOperand &Src = Def->getOperand(1); + if (Src.isUndef()) + return ValueTrackerResult(); return ValueTrackerResult(Src.getReg(), Src.getSubReg()); } @@ -1925,6 +1927,8 @@ ValueTrackerResult ValueTracker::getNextSourceFromBitc } const MachineOperand &Src = Def->getOperand(SrcIdx); + if (Src.isUndef()) + return ValueTrackerResult(); return ValueTrackerResult(Src.getReg(), Src.getSubReg()); } @@ -2093,6 +2097,10 @@ ValueTrackerResult ValueTracker::getNextSourceFromPHI( for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) { auto &MO = Def->getOperand(i); assert(MO.isReg() && "Invalid PHI instruction"); + // We have no code to deal with undef operands. They shouldn't happen in + // normal programs anyway. + if (MO.isUndef()) + return ValueTrackerResult(); Res.addSource(MO.getReg(), MO.getSubReg()); } @@ -2149,9 +2157,14 @@ ValueTrackerResult ValueTracker::getNextSource() { // If we can still move up in the use-def chain, move to the next // definition. if (!TargetRegisterInfo::isPhysicalRegister(Reg) && OneRegSrc) { - Def = MRI.getVRegDef(Reg); - DefIdx = MRI.def_begin(Reg).getOperandNo(); - DefSubReg = Res.getSrcSubReg(0); + MachineRegisterInfo::def_iterator DI = MRI.def_begin(Reg); + if (DI != MRI.def_end()) { + Def = DI->getParent(); + DefIdx = DI.getOperandNo(); + DefSubReg = Res.getSrcSubReg(0); + } else { + Def = nullptr; + } return Res; } } Modified: vendor/llvm/dist-release_60/lib/CodeGen/TargetInstrInfo.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/TargetInstrInfo.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/CodeGen/TargetInstrInfo.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -1151,6 +1151,8 @@ bool TargetInstrInfo::getRegSequenceInputs( for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx; OpIdx += 2) { const MachineOperand &MOReg = MI.getOperand(OpIdx); + if (MOReg.isUndef()) + continue; const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1); assert(MOSubIdx.isImm() && "One of the subindex of the reg_sequence is not an immediate"); @@ -1174,6 +1176,8 @@ bool TargetInstrInfo::getExtractSubregInputs( // Def = EXTRACT_SUBREG v0.sub1, sub0. assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def"); const MachineOperand &MOReg = MI.getOperand(1); + if (MOReg.isUndef()) + return false; const MachineOperand &MOSubIdx = MI.getOperand(2); assert(MOSubIdx.isImm() && "The subindex of the extract_subreg is not an immediate"); @@ -1198,6 +1202,8 @@ bool TargetInstrInfo::getInsertSubregInputs( assert(DefIdx == 0 && "INSERT_SUBREG only has one def"); const MachineOperand &MOBaseReg = MI.getOperand(1); const MachineOperand &MOInsertedReg = MI.getOperand(2); + if (MOInsertedReg.isUndef()) + return false; const MachineOperand &MOSubIdx = MI.getOperand(3); assert(MOSubIdx.isImm() && "One of the subindex of the reg_sequence is not an immediate"); Modified: vendor/llvm/dist-release_60/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -1422,7 +1422,8 @@ RuntimeDyldELF::processRelocationRef( SectionEntry &Section = Sections[SectionID]; uint8_t *Target = Section.getAddressWithOffset(Offset); bool RangeOverflow = false; - if (!Value.SymbolName && SymType != SymbolRef::ST_Unknown) { + bool IsExtern = Value.SymbolName || SymType == SymbolRef::ST_Unknown; + if (!IsExtern) { if (AbiVariant != 2) { // In the ELFv1 ABI, a function call may point to the .opd entry, // so the final symbol value is calculated based on the relocation @@ -1432,21 +1433,24 @@ RuntimeDyldELF::processRelocationRef( } else { // In the ELFv2 ABI, a function symbol may provide a local entry // point, which must be used for direct calls. - uint8_t SymOther = Symbol->getOther(); - Value.Addend += ELF::decodePPC64LocalEntryOffset(SymOther); + if (Value.SectionID == SectionID){ + uint8_t SymOther = Symbol->getOther(); + Value.Addend += ELF::decodePPC64LocalEntryOffset(SymOther); + } } uint8_t *RelocTarget = Sections[Value.SectionID].getAddressWithOffset(Value.Addend); int64_t delta = static_cast(Target - RelocTarget); // If it is within 26-bits branch range, just set the branch target - if (SignExtend64<26>(delta) == delta) { + if (SignExtend64<26>(delta) != delta) { + RangeOverflow = true; + } else if ((AbiVariant != 2) || + (AbiVariant == 2 && Value.SectionID == SectionID)) { RelocationEntry RE(SectionID, Offset, RelType, Value.Addend); addRelocationForSection(RE, Value.SectionID); - } else { - RangeOverflow = true; } } - if (Value.SymbolName || SymType == SymbolRef::ST_Unknown || + if (IsExtern || (AbiVariant == 2 && Value.SectionID != SectionID) || RangeOverflow) { // It is an external symbol (either Value.SymbolName is set, or // SymType is SymbolRef::ST_Unknown) or out of range. @@ -1503,10 +1507,10 @@ RuntimeDyldELF::processRelocationRef( RelType, 0); Section.advanceStubOffset(getMaxStubSize()); } - if (Value.SymbolName || SymType == SymbolRef::ST_Unknown) { + if (IsExtern || (AbiVariant == 2 && Value.SectionID != SectionID)) { // Restore the TOC for external calls if (AbiVariant == 2) - writeInt32BE(Target + 4, 0xE8410018); // ld r2,28(r1) + writeInt32BE(Target + 4, 0xE8410018); // ld r2,24(r1) else writeInt32BE(Target + 4, 0xE8410028); // ld r2,40(r1) } Modified: vendor/llvm/dist-release_60/lib/IR/Core.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/IR/Core.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/IR/Core.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -359,11 +359,9 @@ LLVMContextRef LLVMGetTypeContext(LLVMTypeRef Ty) { return wrap(&unwrap(Ty)->getContext()); } -#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) -LLVM_DUMP_METHOD void LLVMDumpType(LLVMTypeRef Ty) { - return unwrap(Ty)->dump(); +void LLVMDumpType(LLVMTypeRef Ty) { + return unwrap(Ty)->print(errs(), /*IsForDebug=*/true); } -#endif char *LLVMPrintTypeToString(LLVMTypeRef Ty) { std::string buf; @@ -658,7 +656,7 @@ void LLVMSetValueName(LLVMValueRef Val, const char *Na unwrap(Val)->setName(Name); } -LLVM_DUMP_METHOD void LLVMDumpValue(LLVMValueRef Val) { +void LLVMDumpValue(LLVMValueRef Val) { unwrap(Val)->print(errs(), /*IsForDebug=*/true); } Modified: vendor/llvm/dist-release_60/lib/MC/MCObjectFileInfo.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/MCObjectFileInfo.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/MC/MCObjectFileInfo.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -289,6 +289,8 @@ void MCObjectFileInfo::initELFMCObjectFileInfo(const T case Triple::mips64el: FDECFIEncoding = dwarf::DW_EH_PE_sdata8; break; + case Triple::ppc64: + case Triple::ppc64le: case Triple::x86_64: FDECFIEncoding = dwarf::DW_EH_PE_pcrel | (Large ? dwarf::DW_EH_PE_sdata8 : dwarf::DW_EH_PE_sdata4); Modified: vendor/llvm/dist-release_60/lib/Support/CMakeLists.txt ============================================================================== --- vendor/llvm/dist-release_60/lib/Support/CMakeLists.txt Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Support/CMakeLists.txt Wed Jun 27 19:14:09 2018 (r335720) @@ -13,8 +13,13 @@ elseif( CMAKE_HOST_UNIX ) if( HAVE_LIBDL ) set(system_libs ${system_libs} ${CMAKE_DL_LIBS}) endif() - if( HAVE_BACKTRACE ) - set(system_libs ${system_libs} ${Backtrace_LIBRARIES}) + if( HAVE_BACKTRACE AND NOT "${Backtrace_LIBRARIES}" STREQUAL "" ) + # On BSDs, CMake returns a fully qualified path to the backtrace library. + # We need to remove the path and the 'lib' prefix, to make it look like a + # regular short library name, suitable for appending to a -l link flag. + get_filename_component(Backtrace_LIBFILE ${Backtrace_LIBRARIES} NAME_WE) + STRING(REGEX REPLACE "^lib" "" Backtrace_LIBFILE ${Backtrace_LIBFILE}) + set(system_libs ${system_libs} ${Backtrace_LIBFILE}) endif() if(LLVM_ENABLE_TERMINFO) if(HAVE_TERMINFO) Modified: vendor/llvm/dist-release_60/lib/Support/Host.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Support/Host.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Support/Host.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -1009,7 +1009,7 @@ StringRef sys::getHostCPUName() { #include "llvm/Support/X86TargetParser.def" // Now check types. -#define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ +#define X86_CPU_TYPE(ARCHNAME, ENUM) \ if (Type == X86::ENUM) \ return ARCHNAME; #include "llvm/Support/X86TargetParser.def" Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64AsmPrinter.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64AsmPrinter.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64AsmPrinter.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -299,6 +299,11 @@ void AArch64AsmPrinter::printOperand(const MachineInst printOffset(MO.getOffset(), O); break; } + case MachineOperand::MO_BlockAddress: { + MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress()); + Sym->print(O, MAI); + break; + } } } Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -46,6 +46,7 @@ #include "llvm/Pass.h" #include "llvm/Support/Casting.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/DebugCounter.h" #include "llvm/Support/raw_ostream.h" #include #include @@ -60,6 +61,8 @@ STATISTIC(NumCollisionsAvoided, "Number of HW prefetch tag collisions avoided"); STATISTIC(NumCollisionsNotAvoided, "Number of HW prefetch tag collisions not avoided due to lack of regsiters"); +DEBUG_COUNTER(FixCounter, "falkor-hwpf", + "Controls which tag collisions are avoided"); namespace { @@ -728,6 +731,21 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineF bool Fixed = false; DEBUG(dbgs() << "Attempting to fix tag collision: " << MI); + + if (!DebugCounter::shouldExecute(FixCounter)) { + DEBUG(dbgs() << "Skipping fix due to debug counter:\n " << MI); + continue; + } + + // Add the non-base registers of MI as live so we don't use them as + // scratch registers. + for (unsigned OpI = 0, OpE = MI.getNumOperands(); OpI < OpE; ++OpI) { + if (OpI == static_cast(LdI.BaseRegIdx)) + continue; + MachineOperand &MO = MI.getOperand(OpI); + if (MO.isReg() && MO.readsReg()) + LR.addReg(MO.getReg()); + } for (unsigned ScratchReg : AArch64::GPR64RegClass) { if (!LR.available(ScratchReg) || MRI.isReserved(ScratchReg)) Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FrameLowering.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FrameLowering.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FrameLowering.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -917,6 +917,8 @@ int AArch64FrameLowering::resolveFrameIndexReference(c int FPOffset = MFI.getObjectOffset(FI) + FixedObject + 16; int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize(); bool isFixed = MFI.isFixedObjectIndex(FI); + bool isCSR = !isFixed && MFI.getObjectOffset(FI) >= + -((int)AFI->getCalleeSavedStackSize()); // Use frame pointer to reference fixed objects. Use it for locals if // there are VLAs or a dynamically realigned SP (and thus the SP isn't @@ -930,6 +932,12 @@ int AArch64FrameLowering::resolveFrameIndexReference(c // Argument access should always use the FP. if (isFixed) { UseFP = hasFP(MF); + } else if (isCSR && RegInfo->needsStackRealignment(MF)) { + // References to the CSR area must use FP if we're re-aligning the stack + // since the dynamically-sized alignment padding is between the SP/BP and + // the CSR area. + assert(hasFP(MF) && "Re-aligned stack must have frame pointer"); + UseFP = true; } else if (hasFP(MF) && !RegInfo->hasBasePointer(MF) && !RegInfo->needsStackRealignment(MF)) { // Use SP or FP, whichever gives us the best chance of the offset @@ -947,9 +955,9 @@ int AArch64FrameLowering::resolveFrameIndexReference(c } } - assert((isFixed || !RegInfo->needsStackRealignment(MF) || !UseFP) && + assert(((isFixed || isCSR) || !RegInfo->needsStackRealignment(MF) || !UseFP) && "In the presence of dynamic stack pointer realignment, " - "non-argument objects cannot be accessed through the frame pointer"); + "non-argument/CSR objects cannot be accessed through the frame pointer"); if (UseFP) { FrameReg = RegInfo->getFrameRegister(MF); Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64ISelLowering.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64ISelLowering.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64ISelLowering.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -4930,7 +4930,8 @@ bool AArch64TargetLowering::isOffsetFoldingLegal( bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases. // FIXME: We should be able to handle f128 as well with a clever lowering. - if (Imm.isPosZero() && (VT == MVT::f16 || VT == MVT::f64 || VT == MVT::f32)) { + if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32 || + (VT == MVT::f16 && Subtarget->hasFullFP16()))) { DEBUG(dbgs() << "Legal fp imm: materialize 0 using the zero register\n"); return true; } @@ -5066,7 +5067,7 @@ SDValue AArch64TargetLowering::getRecipEstimate(SDValu // Table of Constraints // TODO: This is the current set of constraints supported by ARM for the -// compiler, not all of them may make sense, e.g. S may be difficult to support. +// compiler, not all of them may make sense. // // r - A general register // w - An FP/SIMD register of some size in the range v0-v31 @@ -5126,6 +5127,8 @@ AArch64TargetLowering::getConstraintType(StringRef Con // currently handle addresses it is the same as 'r'. case 'Q': return C_Memory; + case 'S': // A symbolic address + return C_Other; } } return TargetLowering::getConstraintType(Constraint); @@ -5250,6 +5253,23 @@ void AArch64TargetLowering::LowerAsmOperandForConstrai Result = DAG.getRegister(AArch64::WZR, MVT::i32); break; } + case 'S': { + // An absolute symbolic address or label reference. + if (const GlobalAddressSDNode *GA = dyn_cast(Op)) { + Result = DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op), + GA->getValueType(0)); + } else if (const BlockAddressSDNode *BA = + dyn_cast(Op)) { + Result = + DAG.getTargetBlockAddress(BA->getBlockAddress(), BA->getValueType(0)); + } else if (const ExternalSymbolSDNode *ES = + dyn_cast(Op)) { + Result = + DAG.getTargetExternalSymbol(ES->getSymbol(), ES->getValueType(0)); + } else + return; + break; + } case 'I': case 'J': @@ -9637,6 +9657,15 @@ static SDValue performPostLD1Combine(SDNode *N, if (LD->getOpcode() != ISD::LOAD) return SDValue(); + // The vector lane must be a constant in the LD1LANE opcode. + SDValue Lane; + if (IsLaneOp) { + Lane = N->getOperand(2); + auto *LaneC = dyn_cast(Lane); + if (!LaneC || LaneC->getZExtValue() >= VT.getVectorNumElements()) + return SDValue(); + } + LoadSDNode *LoadSDN = cast(LD); EVT MemVT = LoadSDN->getMemoryVT(); // Check if memory operand is the same type as the vector element. @@ -9693,7 +9722,7 @@ static SDValue performPostLD1Combine(SDNode *N, Ops.push_back(LD->getOperand(0)); // Chain if (IsLaneOp) { Ops.push_back(Vector); // The vector to be inserted - Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector + Ops.push_back(Lane); // The lane to be inserted in the vector } Ops.push_back(Addr); Ops.push_back(Inc); Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstrInfo.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstrInfo.td Wed Jun 27 19:14:09 2018 (r335720) @@ -2713,7 +2713,7 @@ defm FMOV : UnscaledConversion<"fmov">; // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1 in { def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>, - Sched<[WriteF]>; + Sched<[WriteF]>, Requires<[HasFullFP16]>; def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>, Sched<[WriteF]>; def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>, Modified: vendor/llvm/dist-release_60/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -147,6 +147,7 @@ extern "C" void LLVMInitializeAMDGPUTarget() { initializeR600PacketizerPass(*PR); initializeR600ExpandSpecialInstrsPassPass(*PR); initializeR600VectorRegMergerPass(*PR); + initializeGlobalISel(*PR); initializeAMDGPUDAGToDAGISelPass(*PR); initializeSILowerI1CopiesPass(*PR); initializeSIFixSGPRCopiesPass(*PR); Modified: vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIISelLowering.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIISelLowering.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIISelLowering.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -358,6 +358,7 @@ SITargetLowering::SITargetLowering(const TargetMachine setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote); setOperationAction(ISD::CTLZ, MVT::i16, Promote); setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote); + setOperationAction(ISD::CTPOP, MVT::i16, Promote); setOperationAction(ISD::SELECT_CC, MVT::i16, Expand); Modified: vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInstructions.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInstructions.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInstructions.td Wed Jun 27 19:14:09 2018 (r335720) @@ -726,6 +726,10 @@ def : GCNPat < (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)), (V_BCNT_U32_B32_e64 $popcnt, $val) >; +def : GCNPat < + (i16 (add (i16 (trunc (ctpop i32:$popcnt))), i16:$val)), + (V_BCNT_U32_B32_e64 $popcnt, $val) +>; /********** ============================================ **********/ /********** Extraction, Insertion, Building and Casting **********/ Modified: vendor/llvm/dist-release_60/lib/Target/ARM/ARMBaseInstrInfo.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -4864,12 +4864,14 @@ bool ARMBaseInstrInfo::getRegSequenceLikeInputs( // Populate the InputRegs accordingly. // rY const MachineOperand *MOReg = &MI.getOperand(1); - InputRegs.push_back( - RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0)); + if (!MOReg->isUndef()) + InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), + MOReg->getSubReg(), ARM::ssub_0)); // rZ MOReg = &MI.getOperand(2); - InputRegs.push_back( - RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1)); + if (!MOReg->isUndef()) + InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), + MOReg->getSubReg(), ARM::ssub_1)); return true; } llvm_unreachable("Target dependent opcode missing"); @@ -4888,6 +4890,8 @@ bool ARMBaseInstrInfo::getExtractSubregLikeInputs( // rX = EXTRACT_SUBREG dZ, ssub_0 // rY = EXTRACT_SUBREG dZ, ssub_1 const MachineOperand &MOReg = MI.getOperand(2); + if (MOReg.isUndef()) + return false; InputReg.Reg = MOReg.getReg(); InputReg.SubReg = MOReg.getSubReg(); InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1; @@ -4907,6 +4911,8 @@ bool ARMBaseInstrInfo::getInsertSubregLikeInputs( // dX = VSETLNi32 dY, rZ, imm const MachineOperand &MOBaseReg = MI.getOperand(1); const MachineOperand &MOInsertedReg = MI.getOperand(2); + if (MOInsertedReg.isUndef()) + return false; const MachineOperand &MOIndex = MI.getOperand(3); BaseReg.Reg = MOBaseReg.getReg(); BaseReg.SubReg = MOBaseReg.getSubReg(); Modified: vendor/llvm/dist-release_60/lib/Target/ARM/ARMComputeBlockSize.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/ARM/ARMComputeBlockSize.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/ARM/ARMComputeBlockSize.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -35,6 +35,7 @@ mayOptimizeThumb2Instruction(const MachineInstr *MI) { case ARM::tBcc: // optimizeThumb2JumpTables. case ARM::t2BR_JT: + case ARM::tBR_JTr: return true; } return false; Modified: vendor/llvm/dist-release_60/lib/Target/Mips/AsmParser/MipsAsmParser.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -5136,6 +5136,7 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCIn // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction // and registers Rd and Base for microMIPS lwp instruction case Mips::JALR_HB: + case Mips::JALR_HB64: case Mips::JALRC_HB_MMR6: case Mips::JALRC_MMR6: if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) Modified: vendor/llvm/dist-release_60/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -225,6 +225,8 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext & switch (Kind) { case Mips::fixup_Mips_NONE: return ELF::R_MIPS_NONE; + case FK_Data_1: + report_fatal_error("MIPS does not support one byte relocations"); case Mips::fixup_Mips_16: case FK_Data_2: return IsPCRel ? ELF::R_MIPS_PC16 : ELF::R_MIPS_16; Modified: vendor/llvm/dist-release_60/lib/Target/Mips/MicroMips32r6InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/MicroMips32r6InstrInfo.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/MicroMips32r6InstrInfo.td Wed Jun 27 19:14:09 2018 (r335720) @@ -1886,6 +1886,12 @@ let AddedComplexity = 41 in { def TAILCALL_MMR6 : TailCall, ISA_MICROMIPS32R6; +def TAILCALLREG_MMR6 : TailCallReg, ISA_MICROMIPS32R6; + +def PseudoIndirectBranch_MMR6 : PseudoIndirectBranchBase, + ISA_MICROMIPS32R6; + def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), (TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6; Modified: vendor/llvm/dist-release_60/lib/Target/Mips/MicroMipsInstrInfo.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/MicroMipsInstrInfo.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/MicroMipsInstrInfo.td Wed Jun 27 19:14:09 2018 (r335720) @@ -1003,6 +1003,12 @@ let DecoderNamespace = "MicroMips", Predicates = [InMi def TAILCALL_MM : TailCall, ISA_MIPS1_NOT_32R6_64R6; +def TAILCALLREG_MM : TailCallReg, + ISA_MICROMIPS32_NOT_MIPS32R6; + +def PseudoIndirectBranch_MM : PseudoIndirectBranchBase, + ISA_MICROMIPS32_NOT_MIPS32R6; + let DecoderNamespace = "MicroMips" in { def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware, RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6; Modified: vendor/llvm/dist-release_60/lib/Target/Mips/Mips.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/Mips.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/Mips.td Wed Jun 27 19:14:09 2018 (r335720) @@ -193,6 +193,10 @@ def FeatureMT : SubtargetFeature<"mt", "HasMT", "true" def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true", "Disable use of the jal instruction">; +def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard", + "UseIndirectJumpsHazard", + "true", "Use indirect jump" + " guards to prevent certain speculation based attacks">; //===----------------------------------------------------------------------===// // Mips processors supported. //===----------------------------------------------------------------------===// Modified: vendor/llvm/dist-release_60/lib/Target/Mips/Mips32r6InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/Mips32r6InstrInfo.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/Mips32r6InstrInfo.td Wed Jun 27 19:14:09 2018 (r335720) @@ -1036,3 +1036,42 @@ def : MipsPat<(select i32:$cond, immz, i32:$f), (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6; } + +// Pseudo instructions +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1, + hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in { + class TailCallRegR6 : + PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>, + PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)>; +} + +class PseudoIndirectBranchBaseR6 : + MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], + II_IndirectBranchPseudo>, + PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)> { + let isTerminator=1; + let isBarrier=1; + let hasDelaySlot = 1; + let isBranch = 1; + let isIndirectBranch = 1; + bit isCTI = 1; +} + + +let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, + NoIndirectJumpGuards] in { + def TAILCALLR6REG : TailCallRegR6, ISA_MIPS32R6; + def PseudoIndirectBranchR6 : PseudoIndirectBranchBaseR6, + ISA_MIPS32R6; +} + +let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, + UseIndirectJumpsHazard] in { + def TAILCALLHBR6REG : TailCallReg, ISA_MIPS32R6; + def PseudoIndrectHazardBranchR6 : PseudoIndirectBranchBase, + ISA_MIPS32R6; +} + Modified: vendor/llvm/dist-release_60/lib/Target/Mips/Mips64InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/Mips64InstrInfo.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/Mips64InstrInfo.td Wed Jun 27 19:14:09 2018 (r335720) @@ -240,13 +240,32 @@ let isCodeGenOnly = 1 in { def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>; def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>; def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>; - def JALR64Pseudo : JumpLinkRegPseudo; + let AdditionalPredicates = [NoIndirectJumpGuards] in + def JALR64Pseudo : JumpLinkRegPseudo; } +let AdditionalPredicates = [NotInMicroMips], + DecoderNamespace = "Mips64" in { + def JR_HB64 : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6; + def JALR_HB64 : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32R2; +} +def PseudoReturn64 : PseudoReturnBase; -def TAILCALLREG64 : TailCallReg; +let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, + NoIndirectJumpGuards] in { + def TAILCALLREG64 : TailCallReg, ISA_MIPS3_NOT_32R6_64R6, + PTR_64; + def PseudoIndirectBranch64 : PseudoIndirectBranchBase, + ISA_MIPS3_NOT_32R6_64R6; +} -def PseudoReturn64 : PseudoReturnBase; -def PseudoIndirectBranch64 : PseudoIndirectBranchBase; +let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, + UseIndirectJumpsHazard] in { + def TAILCALLREGHB64 : TailCallReg, + ISA_MIPS32R2_NOT_32R6_64R6, PTR_64; + def PseudoIndirectHazardBranch64 : PseudoIndirectBranchBase, + ISA_MIPS32R2_NOT_32R6_64R6; +} /// Multiply and Divide Instructions. let AdditionalPredicates = [NotInMicroMips] in { @@ -536,6 +555,10 @@ def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd, II_DM ISA_MIPS3; } + +let AdditionalPredicates = [UseIndirectJumpsHazard] in + def JALRHB64Pseudo : JumpLinkRegPseudo; + //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// @@ -843,7 +866,8 @@ let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias<"dext $rt, $rs, $pos, $size", (DEXTU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos, uimm5_plus1:$size), 0>, ISA_MIPS64R2; - + def : MipsInstAlias<"jalr.hb $rs", (JALR_HB64 RA_64, GPR64Opnd:$rs), 1>, + ISA_MIPS64; // Two operand (implicit 0 selector) versions: def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>; Modified: vendor/llvm/dist-release_60/lib/Target/Mips/Mips64r6InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/Mips64r6InstrInfo.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/Mips64r6InstrInfo.td Wed Jun 27 19:14:09 2018 (r335720) @@ -104,6 +104,16 @@ class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jm class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>; class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>; + +class JR_HB64_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR64Opnd> { + bit isBranch = 1; *** DIFF OUTPUT TRUNCATED AT 1000 LINES *** From owner-svn-src-vendor@freebsd.org Wed Jun 27 19:14:38 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 201CA1002F73; Wed, 27 Jun 2018 19:14:38 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id C35278DBA3; Wed, 27 Jun 2018 19:14:37 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 8D2C7272FB; Wed, 27 Jun 2018 19:14:37 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5RJEbf3042948; Wed, 27 Jun 2018 19:14:37 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5RJEWPJ042921; Wed, 27 Jun 2018 19:14:32 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201806271914.w5RJEWPJ042921@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 27 Jun 2018 19:14:32 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335722 - in vendor/clang/dist-release_60: docs include/clang/Basic include/clang/Driver lib/AST lib/Basic lib/Basic/Targets lib/CodeGen lib/Driver lib/Driver/ToolChains lib/Driver/Tool... X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in vendor/clang/dist-release_60: docs include/clang/Basic include/clang/Driver lib/AST lib/Basic lib/Basic/Targets lib/CodeGen lib/Driver lib/Driver/ToolChains lib/Driver/ToolChains/Arch lib/Frontend ... X-SVN-Commit-Revision: 335722 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jun 2018 19:14:38 -0000 Author: dim Date: Wed Jun 27 19:14:32 2018 New Revision: 335722 URL: https://svnweb.freebsd.org/changeset/base/335722 Log: Vendor import of clang 6.0.1 release r335540: https://llvm.org/svn/llvm-project/cfe/tags/RELEASE_601/final@335540 Added: vendor/clang/dist-release_60/test/CodeGen/ms_struct-long-double.c (contents, props changed) vendor/clang/dist-release_60/test/Driver/Inputs/empty.cfg vendor/clang/dist-release_60/test/Driver/config-file4.c (contents, props changed) vendor/clang/dist-release_60/test/Driver/mips-indirect-branch.c (contents, props changed) vendor/clang/dist-release_60/test/Index/Inputs/reparse-issue.h (contents, props changed) vendor/clang/dist-release_60/test/Index/Inputs/reparse-issue.h-0 vendor/clang/dist-release_60/test/Index/Inputs/reparse-issue.h-1 vendor/clang/dist-release_60/test/Index/reparsed-live-issue.cpp (contents, props changed) Modified: vendor/clang/dist-release_60/docs/UsersManual.rst vendor/clang/dist-release_60/include/clang/Basic/DiagnosticDriverKinds.td vendor/clang/dist-release_60/include/clang/Basic/DiagnosticSemaKinds.td vendor/clang/dist-release_60/include/clang/Driver/CLCompatOptions.td vendor/clang/dist-release_60/include/clang/Driver/Options.td vendor/clang/dist-release_60/lib/AST/ExprConstant.cpp vendor/clang/dist-release_60/lib/AST/RecordLayoutBuilder.cpp vendor/clang/dist-release_60/lib/Basic/Targets/AArch64.cpp vendor/clang/dist-release_60/lib/Basic/Targets/Mips.h vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp vendor/clang/dist-release_60/lib/Basic/Targets/X86.h vendor/clang/dist-release_60/lib/Basic/Version.cpp vendor/clang/dist-release_60/lib/CodeGen/TargetInfo.cpp vendor/clang/dist-release_60/lib/Driver/Driver.cpp vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.cpp vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.h vendor/clang/dist-release_60/lib/Driver/ToolChains/Clang.cpp vendor/clang/dist-release_60/lib/Driver/ToolChains/CrossWindows.cpp vendor/clang/dist-release_60/lib/Driver/ToolChains/MinGW.cpp vendor/clang/dist-release_60/lib/Frontend/ASTUnit.cpp vendor/clang/dist-release_60/lib/Frontend/CompilerInvocation.cpp vendor/clang/dist-release_60/lib/Headers/avx512vlbitalgintrin.h vendor/clang/dist-release_60/lib/Headers/avx512vlvbmi2intrin.h vendor/clang/dist-release_60/lib/Headers/avx512vlvnniintrin.h vendor/clang/dist-release_60/lib/Sema/SemaDecl.cpp vendor/clang/dist-release_60/test/CodeGen/aarch64-inline-asm.c vendor/clang/dist-release_60/test/CodeGen/attr-target-x86.c vendor/clang/dist-release_60/test/CodeGen/avx512vlbitalg-builtins.c vendor/clang/dist-release_60/test/CodeGen/avx512vlvbmi2-builtins.c vendor/clang/dist-release_60/test/CodeGen/avx512vlvnni-builtins.c vendor/clang/dist-release_60/test/CodeGen/decl.c vendor/clang/dist-release_60/test/CodeGen/function-attributes.c vendor/clang/dist-release_60/test/CodeGen/mingw-long-double.c vendor/clang/dist-release_60/test/CodeGenCXX/const-init-cxx11.cpp vendor/clang/dist-release_60/test/CodeGenCXX/cxx0x-initializer-references.cpp vendor/clang/dist-release_60/test/CodeGenCXX/cxx0x-initializer-stdinitializerlist.cpp vendor/clang/dist-release_60/test/CodeGenObjCXX/arc-cxx11-init-list.mm vendor/clang/dist-release_60/test/Driver/clang_f_opts.c vendor/clang/dist-release_60/test/Driver/mingw-libgcc.c vendor/clang/dist-release_60/test/Driver/mips-features.c vendor/clang/dist-release_60/test/Driver/windows-cross.c vendor/clang/dist-release_60/test/SemaCXX/constant-expression-cxx11.cpp vendor/clang/dist-release_60/test/SemaCXX/warn-missing-variable-declarations.cpp vendor/clang/dist-release_60/tools/driver/driver.cpp Modified: vendor/clang/dist-release_60/docs/UsersManual.rst ============================================================================== --- vendor/clang/dist-release_60/docs/UsersManual.rst Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/docs/UsersManual.rst Wed Jun 27 19:14:32 2018 (r335722) @@ -2741,7 +2741,7 @@ Execute ``clang-cl /?`` to see a list of supported opt /Gv Set __vectorcall as a default calling convention /Gw- Don't put each data item in its own section /Gw Put each data item in its own section - /GX- Enable exception handling + /GX- Disable exception handling /GX Enable exception handling /Gy- Don't put each function in its own section /Gy Put each function in its own section Modified: vendor/clang/dist-release_60/include/clang/Basic/DiagnosticDriverKinds.td ============================================================================== --- vendor/clang/dist-release_60/include/clang/Basic/DiagnosticDriverKinds.td Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/include/clang/Basic/DiagnosticDriverKinds.td Wed Jun 27 19:14:32 2018 (r335722) @@ -326,6 +326,10 @@ def warn_drv_unsupported_abicalls : Warning< "ignoring '-mabicalls' option as it cannot be used with " "non position-independent code and the N64 ABI">, InGroup; +def err_drv_unsupported_indirect_jump_opt : Error< + "'-mindirect-jump=%0' is unsupported with the '%1' architecture">; +def err_drv_unknown_indirect_jump_opt : Error< + "unknown '-mindirect-jump=' option '%0'">; def warn_drv_unable_to_find_directory_expected : Warning< "unable to find %0 directory, expected to be in '%1'">, Modified: vendor/clang/dist-release_60/include/clang/Basic/DiagnosticSemaKinds.td ============================================================================== --- vendor/clang/dist-release_60/include/clang/Basic/DiagnosticSemaKinds.td Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/include/clang/Basic/DiagnosticSemaKinds.td Wed Jun 27 19:14:32 2018 (r335722) @@ -759,6 +759,10 @@ def warn_cxx_ms_struct : Warning<"ms_struct may not produce Microsoft-compatible layouts for classes " "with base classes or virtual functions">, DefaultError, InGroup; +def warn_npot_ms_struct : + Warning<"ms_struct may not produce Microsoft-compatible layouts with fundamental " + "data types with sizes that aren't a power of two">, + DefaultError, InGroup; def err_section_conflict : Error<"%0 causes a section type conflict with %1">; def err_no_base_classes : Error<"invalid use of '__super', %0 has no base classes">; def err_invalid_super_scope : Error<"invalid use of '__super', " Modified: vendor/clang/dist-release_60/include/clang/Driver/CLCompatOptions.td ============================================================================== --- vendor/clang/dist-release_60/include/clang/Driver/CLCompatOptions.td Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/include/clang/Driver/CLCompatOptions.td Wed Jun 27 19:14:32 2018 (r335722) @@ -238,7 +238,7 @@ def _SLASH_Fo : CLCompileJoined<"Fo">, def _SLASH_GX : CLFlag<"GX">, HelpText<"Enable exception handling">; def _SLASH_GX_ : CLFlag<"GX-">, - HelpText<"Enable exception handling">; + HelpText<"Disable exception handling">; def _SLASH_imsvc : CLJoinedOrSeparate<"imsvc">, HelpText<"Add directory to system include search path, as if part of %INCLUDE%">, MetaVarName<"">; Modified: vendor/clang/dist-release_60/include/clang/Driver/Options.td ============================================================================== --- vendor/clang/dist-release_60/include/clang/Driver/Options.td Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/include/clang/Driver/Options.td Wed Jun 27 19:14:32 2018 (r335722) @@ -1100,7 +1100,8 @@ def fthinlto_index_EQ : Joined<["-"], "fthinlto-index= HelpText<"Perform ThinLTO importing using provided function summary index">; def fmacro_backtrace_limit_EQ : Joined<["-"], "fmacro-backtrace-limit=">, Group, Flags<[DriverOption, CoreOption]>; -def fmerge_all_constants : Flag<["-"], "fmerge-all-constants">, Group; +def fmerge_all_constants : Flag<["-"], "fmerge-all-constants">, Group, + Flags<[CC1Option]>, HelpText<"Allow merging of constants">; def fmessage_length_EQ : Joined<["-"], "fmessage-length=">, Group; def fms_extensions : Flag<["-"], "fms-extensions">, Group, Flags<[CC1Option, CoreOption]>, HelpText<"Accept some non-standard constructs supported by the Microsoft compiler">; @@ -1249,7 +1250,7 @@ def fveclib : Joined<["-"], "fveclib=">, Group, Group, HelpText<"Disallow implicit conversions between vectors with a different number of elements or different element types">, Flags<[CC1Option]>; def fno_merge_all_constants : Flag<["-"], "fno-merge-all-constants">, Group, - Flags<[CC1Option]>, HelpText<"Disallow merging of constants">; + HelpText<"Disallow merging of constants">; def fno_modules : Flag <["-"], "fno-modules">, Group, Flags<[DriverOption]>; def fno_implicit_module_maps : Flag <["-"], "fno-implicit-module-maps">, Group, @@ -1992,6 +1993,9 @@ def mbranch_likely : Flag<["-"], "mbranch-likely">, Gr IgnoredGCCCompat; def mno_branch_likely : Flag<["-"], "mno-branch-likely">, Group, IgnoredGCCCompat; +def mindirect_jump_EQ : Joined<["-"], "mindirect-jump=">, + Group, + HelpText<"Change indirect jump instructions to inhibit speculation">; def mdsp : Flag<["-"], "mdsp">, Group; def mno_dsp : Flag<["-"], "mno-dsp">, Group; def mdspr2 : Flag<["-"], "mdspr2">, Group; @@ -2559,6 +2563,8 @@ def mrtm : Flag<["-"], "mrtm">, Group, Group; def mrdseed : Flag<["-"], "mrdseed">, Group; def mno_rdseed : Flag<["-"], "mno-rdseed">, Group; +def msahf : Flag<["-"], "msahf">, Group; +def mno_sahf : Flag<["-"], "mno-sahf">, Group; def msgx : Flag<["-"], "msgx">, Group; def mno_sgx : Flag<["-"], "mno-sgx">, Group; def msha : Flag<["-"], "msha">, Group; Modified: vendor/clang/dist-release_60/lib/AST/ExprConstant.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/AST/ExprConstant.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/AST/ExprConstant.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -61,14 +61,22 @@ namespace { static QualType getType(APValue::LValueBase B) { if (!B) return QualType(); - if (const ValueDecl *D = B.dyn_cast()) + if (const ValueDecl *D = B.dyn_cast()) { // FIXME: It's unclear where we're supposed to take the type from, and - // this actually matters for arrays of unknown bound. Using the type of - // the most recent declaration isn't clearly correct in general. Eg: + // this actually matters for arrays of unknown bound. Eg: // // extern int arr[]; void f() { extern int arr[3]; }; // constexpr int *p = &arr[1]; // valid? - return cast(D->getMostRecentDecl())->getType(); + // + // For now, we take the array bound from the most recent declaration. + for (auto *Redecl = cast(D->getMostRecentDecl()); Redecl; + Redecl = cast_or_null(Redecl->getPreviousDecl())) { + QualType T = Redecl->getType(); + if (!T->isIncompleteArrayType()) + return T; + } + return D->getType(); + } const Expr *Base = B.get(); @@ -8535,9 +8543,6 @@ bool IntExprEvaluator::VisitBinaryOperator(const Binar (LHSValue.Base && isZeroSized(RHSValue))) return Error(E); // Pointers with different bases cannot represent the same object. - // (Note that clang defaults to -fmerge-all-constants, which can - // lead to inconsistent results for comparisons involving the address - // of a constant; this generally doesn't matter in practice.) return Success(E->getOpcode() == BO_NE, E); } Modified: vendor/clang/dist-release_60/lib/AST/RecordLayoutBuilder.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/AST/RecordLayoutBuilder.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/AST/RecordLayoutBuilder.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -1751,7 +1751,34 @@ void ItaniumRecordLayoutBuilder::LayoutField(const Fie QualType T = Context.getBaseElementType(D->getType()); if (const BuiltinType *BTy = T->getAs()) { CharUnits TypeSize = Context.getTypeSizeInChars(BTy); - if (TypeSize > FieldAlign) + + if (!llvm::isPowerOf2_64(TypeSize.getQuantity())) { + assert( + !Context.getTargetInfo().getTriple().isWindowsMSVCEnvironment() && + "Non PowerOf2 size in MSVC mode"); + // Base types with sizes that aren't a power of two don't work + // with the layout rules for MS structs. This isn't an issue in + // MSVC itself since there are no such base data types there. + // On e.g. x86_32 mingw and linux, long double is 12 bytes though. + // Any structs involving that data type obviously can't be ABI + // compatible with MSVC regardless of how it is laid out. + + // Since ms_struct can be mass enabled (via a pragma or via the + // -mms-bitfields command line parameter), this can trigger for + // structs that don't actually need MSVC compatibility, so we + // need to be able to sidestep the ms_struct layout for these types. + + // Since the combination of -mms-bitfields together with structs + // like max_align_t (which contains a long double) for mingw is + // quite comon (and GCC handles it silently), just handle it + // silently there. For other targets that have ms_struct enabled + // (most probably via a pragma or attribute), trigger a diagnostic + // that defaults to an error. + if (!Context.getTargetInfo().getTriple().isWindowsGNUEnvironment()) + Diag(D->getLocation(), diag::warn_npot_ms_struct); + } + if (TypeSize > FieldAlign && + llvm::isPowerOf2_64(TypeSize.getQuantity())) FieldAlign = TypeSize; } } Modified: vendor/clang/dist-release_60/lib/Basic/Targets/AArch64.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Basic/Targets/AArch64.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Basic/Targets/AArch64.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -299,7 +299,40 @@ ArrayRef AArch64TargetInfo::getGCCRegNam } const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { - {{"w31"}, "wsp"}, {{"x29"}, "fp"}, {{"x30"}, "lr"}, {{"x31"}, "sp"}, + {{"w31"}, "wsp"}, + {{"x31"}, "sp"}, + // GCC rN registers are aliases of xN registers. + {{"r0"}, "x0"}, + {{"r1"}, "x1"}, + {{"r2"}, "x2"}, + {{"r3"}, "x3"}, + {{"r4"}, "x4"}, + {{"r5"}, "x5"}, + {{"r6"}, "x6"}, + {{"r7"}, "x7"}, + {{"r8"}, "x8"}, + {{"r9"}, "x9"}, + {{"r10"}, "x10"}, + {{"r11"}, "x11"}, + {{"r12"}, "x12"}, + {{"r13"}, "x13"}, + {{"r14"}, "x14"}, + {{"r15"}, "x15"}, + {{"r16"}, "x16"}, + {{"r17"}, "x17"}, + {{"r18"}, "x18"}, + {{"r19"}, "x19"}, + {{"r20"}, "x20"}, + {{"r21"}, "x21"}, + {{"r22"}, "x22"}, + {{"r23"}, "x23"}, + {{"r24"}, "x24"}, + {{"r25"}, "x25"}, + {{"r26"}, "x26"}, + {{"r27"}, "x27"}, + {{"r28"}, "x28"}, + {{"r29", "x29"}, "fp"}, + {{"r30", "x30"}, "lr"}, // The S/D/Q and W/X registers overlap, but aren't really aliases; we // don't want to substitute one of these for a different-sized one. }; Modified: vendor/clang/dist-release_60/lib/Basic/Targets/Mips.h ============================================================================== --- vendor/clang/dist-release_60/lib/Basic/Targets/Mips.h Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Basic/Targets/Mips.h Wed Jun 27 19:14:32 2018 (r335722) @@ -54,6 +54,7 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public enum DspRevEnum { NoDSP, DSP1, DSP2 } DspRev; bool HasMSA; bool DisableMadd4; + bool UseIndirectJumpHazard; protected: bool HasFP64; @@ -64,7 +65,8 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public : TargetInfo(Triple), IsMips16(false), IsMicromips(false), IsNan2008(false), IsAbs2008(false), IsSingleFloat(false), IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat), - DspRev(NoDSP), HasMSA(false), DisableMadd4(false), HasFP64(false) { + DspRev(NoDSP), HasMSA(false), DisableMadd4(false), + UseIndirectJumpHazard(false), HasFP64(false) { TheCXXABI.set(TargetCXXABI::GenericMIPS); setABI((getTriple().getArch() == llvm::Triple::mips || @@ -338,6 +340,8 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public IsAbs2008 = false; else if (Feature == "+noabicalls") IsNoABICalls = true; + else if (Feature == "+use-indirect-jump-hazard") + UseIndirectJumpHazard = true; } setDataLayout(); Modified: vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Basic/Targets/X86.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -198,6 +198,7 @@ bool X86TargetInfo::initFeatureMap( LLVM_FALLTHROUGH; case CK_Core2: setFeatureEnabledImpl(Features, "ssse3", true); + setFeatureEnabledImpl(Features, "sahf", true); LLVM_FALLTHROUGH; case CK_Yonah: case CK_Prescott: @@ -239,6 +240,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "ssse3", true); setFeatureEnabledImpl(Features, "fxsr", true); setFeatureEnabledImpl(Features, "cx16", true); + setFeatureEnabledImpl(Features, "sahf", true); break; case CK_KNM: @@ -269,6 +271,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "xsaveopt", true); setFeatureEnabledImpl(Features, "xsave", true); setFeatureEnabledImpl(Features, "movbe", true); + setFeatureEnabledImpl(Features, "sahf", true); break; case CK_K6_2: @@ -282,6 +285,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "sse4a", true); setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "popcnt", true); + setFeatureEnabledImpl(Features, "sahf", true); LLVM_FALLTHROUGH; case CK_K8SSE3: setFeatureEnabledImpl(Features, "sse3", true); @@ -315,6 +319,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "prfchw", true); setFeatureEnabledImpl(Features, "cx16", true); setFeatureEnabledImpl(Features, "fxsr", true); + setFeatureEnabledImpl(Features, "sahf", true); break; case CK_ZNVER1: @@ -338,6 +343,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "prfchw", true); setFeatureEnabledImpl(Features, "rdrnd", true); setFeatureEnabledImpl(Features, "rdseed", true); + setFeatureEnabledImpl(Features, "sahf", true); setFeatureEnabledImpl(Features, "sha", true); setFeatureEnabledImpl(Features, "sse4a", true); setFeatureEnabledImpl(Features, "xsave", true); @@ -372,6 +378,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "cx16", true); setFeatureEnabledImpl(Features, "fxsr", true); setFeatureEnabledImpl(Features, "xsave", true); + setFeatureEnabledImpl(Features, "sahf", true); break; } if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) @@ -768,6 +775,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector(Feature) @@ -1240,6 +1249,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) .Case("rdrnd", true) .Case("rdseed", true) .Case("rtm", true) + .Case("sahf", true) .Case("sgx", true) .Case("sha", true) .Case("shstk", true) @@ -1313,6 +1323,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) cons .Case("retpoline", HasRetpoline) .Case("retpoline-external-thunk", HasRetpolineExternalThunk) .Case("rtm", HasRTM) + .Case("sahf", HasLAHFSAHF) .Case("sgx", HasSGX) .Case("sha", HasSHA) .Case("shstk", HasSHSTK) Modified: vendor/clang/dist-release_60/lib/Basic/Targets/X86.h ============================================================================== --- vendor/clang/dist-release_60/lib/Basic/Targets/X86.h Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Basic/Targets/X86.h Wed Jun 27 19:14:32 2018 (r335722) @@ -98,6 +98,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public T bool HasPREFETCHWT1 = false; bool HasRetpoline = false; bool HasRetpolineExternalThunk = false; + bool HasLAHFSAHF = false; /// \brief Enumeration of all of the X86 CPUs supported by Clang. /// Modified: vendor/clang/dist-release_60/lib/Basic/Version.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Basic/Version.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Basic/Version.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -36,7 +36,7 @@ std::string getClangRepositoryPath() { // If the SVN_REPOSITORY is empty, try to use the SVN keyword. This helps us // pick up a tag in an SVN export, for example. - StringRef SVNRepository("$URL: https://llvm.org/svn/llvm-project/cfe/tags/RELEASE_600/final/lib/Basic/Version.cpp $"); + StringRef SVNRepository("$URL: https://llvm.org/svn/llvm-project/cfe/tags/RELEASE_601/final/lib/Basic/Version.cpp $"); if (URL.empty()) { URL = SVNRepository.slice(SVNRepository.find(':'), SVNRepository.find("/lib/Basic")); Modified: vendor/clang/dist-release_60/lib/CodeGen/TargetInfo.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/CodeGen/TargetInfo.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/CodeGen/TargetInfo.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -1931,13 +1931,8 @@ void X86_32TargetCodeGenInfo::setTargetAttributes( return; if (const FunctionDecl *FD = dyn_cast_or_null(D)) { if (FD->hasAttr()) { - // Get the LLVM function. llvm::Function *Fn = cast(GV); - - // Now add the 'alignstack' attribute with a value of 16. - llvm::AttrBuilder B; - B.addStackAlignmentAttr(16); - Fn->addAttributes(llvm::AttributeList::FunctionIndex, B); + Fn->addFnAttr("stackrealign"); } if (FD->hasAttr()) { llvm::Function *Fn = cast(GV); @@ -2292,13 +2287,8 @@ class X86_64TargetCodeGenInfo : public TargetCodeGenIn return; if (const FunctionDecl *FD = dyn_cast_or_null(D)) { if (FD->hasAttr()) { - // Get the LLVM function. - auto *Fn = cast(GV); - - // Now add the 'alignstack' attribute with a value of 16. - llvm::AttrBuilder B; - B.addStackAlignmentAttr(16); - Fn->addAttributes(llvm::AttributeList::FunctionIndex, B); + llvm::Function *Fn = cast(GV); + Fn->addFnAttr("stackrealign"); } if (FD->hasAttr()) { llvm::Function *Fn = cast(GV); @@ -2429,13 +2419,8 @@ void WinX86_64TargetCodeGenInfo::setTargetAttributes( return; if (const FunctionDecl *FD = dyn_cast_or_null(D)) { if (FD->hasAttr()) { - // Get the LLVM function. - auto *Fn = cast(GV); - - // Now add the 'alignstack' attribute with a value of 16. - llvm::AttrBuilder B; - B.addStackAlignmentAttr(16); - Fn->addAttributes(llvm::AttributeList::FunctionIndex, B); + llvm::Function *Fn = cast(GV); + Fn->addFnAttr("stackrealign"); } if (FD->hasAttr()) { llvm::Function *Fn = cast(GV); Modified: vendor/clang/dist-release_60/lib/Driver/Driver.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Driver/Driver.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Driver/Driver.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -858,11 +858,14 @@ Compilation *Driver::BuildCompilation(ArrayRefgetOption().matches(options::OPT_config)) + continue; + unsigned Index = Args.MakeIndex(Opt->getSpelling()); const Arg *BaseArg = &Opt->getBaseArg(); if (BaseArg == Opt) BaseArg = nullptr; Arg *Copy = new llvm::opt::Arg(Opt->getOption(), Opt->getSpelling(), - Args.size(), BaseArg); + Index, BaseArg); Copy->getValues() = Opt->getValues(); if (Opt->isClaimed()) Copy->claim(); Modified: vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -343,6 +343,28 @@ void mips::getMIPSTargetFeatures(const Driver &D, cons AddTargetFeature(Args, Features, options::OPT_mno_madd4, options::OPT_mmadd4, "nomadd4"); AddTargetFeature(Args, Features, options::OPT_mmt, options::OPT_mno_mt, "mt"); + + if (Arg *A = Args.getLastArg(options::OPT_mindirect_jump_EQ)) { + StringRef Val = StringRef(A->getValue()); + if (Val == "hazard") { + Arg *B = + Args.getLastArg(options::OPT_mmicromips, options::OPT_mno_micromips); + Arg *C = Args.getLastArg(options::OPT_mips16, options::OPT_mno_mips16); + + if (B && B->getOption().matches(options::OPT_mmicromips)) + D.Diag(diag::err_drv_unsupported_indirect_jump_opt) + << "hazard" << "micromips"; + else if (C && C->getOption().matches(options::OPT_mips16)) + D.Diag(diag::err_drv_unsupported_indirect_jump_opt) + << "hazard" << "mips16"; + else if (mips::supportsIndirectJumpHazardBarrier(CPUName)) + Features.push_back("+use-indirect-jump-hazard"); + else + D.Diag(diag::err_drv_unsupported_indirect_jump_opt) + << "hazard" << CPUName; + } else + D.Diag(diag::err_drv_unknown_indirect_jump_opt) << Val; + } } mips::IEEE754Standard mips::getIEEE754Standard(StringRef &CPU) { @@ -446,4 +468,21 @@ bool mips::shouldUseFPXX(const ArgList &Args, const ll UseFPXX = false; return UseFPXX; +} + +bool mips::supportsIndirectJumpHazardBarrier(StringRef &CPU) { + // Supporting the hazard barrier method of dealing with indirect + // jumps requires MIPSR2 support. + return llvm::StringSwitch(CPU) + .Case("mips32r2", true) + .Case("mips32r3", true) + .Case("mips32r5", true) + .Case("mips32r6", true) + .Case("mips64r2", true) + .Case("mips64r3", true) + .Case("mips64r5", true) + .Case("mips64r6", true) + .Case("octeon", true) + .Case("p5600", true) + .Default(false); } Modified: vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.h ============================================================================== --- vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.h Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Driver/ToolChains/Arch/Mips.h Wed Jun 27 19:14:32 2018 (r335722) @@ -53,6 +53,7 @@ bool isFPXXDefault(const llvm::Triple &Triple, StringR bool shouldUseFPXX(const llvm::opt::ArgList &Args, const llvm::Triple &Triple, StringRef CPUName, StringRef ABIName, mips::FloatABI FloatABI); +bool supportsIndirectJumpHazardBarrier(StringRef &CPU); } // end namespace mips } // end namespace target Modified: vendor/clang/dist-release_60/lib/Driver/ToolChains/Clang.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Driver/ToolChains/Clang.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Driver/ToolChains/Clang.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -3288,9 +3288,9 @@ void Clang::ConstructJob(Compilation &C, const JobActi Args.AddLastArg(CmdArgs, options::OPT_fveclib); - if (!Args.hasFlag(options::OPT_fmerge_all_constants, - options::OPT_fno_merge_all_constants)) - CmdArgs.push_back("-fno-merge-all-constants"); + if (Args.hasFlag(options::OPT_fmerge_all_constants, + options::OPT_fno_merge_all_constants, false)) + CmdArgs.push_back("-fmerge-all-constants"); // LLVM Code Generator Options. Modified: vendor/clang/dist-release_60/lib/Driver/ToolChains/CrossWindows.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Driver/ToolChains/CrossWindows.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Driver/ToolChains/CrossWindows.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -127,7 +127,8 @@ void tools::CrossWindows::Linker::ConstructJob( } CmdArgs.push_back("-shared"); - CmdArgs.push_back("-Bdynamic"); + CmdArgs.push_back(Args.hasArg(options::OPT_static) ? "-Bstatic" + : "-Bdynamic"); CmdArgs.push_back("--enable-auto-image-base"); Modified: vendor/clang/dist-release_60/lib/Driver/ToolChains/MinGW.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Driver/ToolChains/MinGW.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Driver/ToolChains/MinGW.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -141,22 +141,21 @@ void tools::MinGW::Linker::ConstructJob(Compilation &C CmdArgs.push_back("console"); } + if (Args.hasArg(options::OPT_mdll)) + CmdArgs.push_back("--dll"); + else if (Args.hasArg(options::OPT_shared)) + CmdArgs.push_back("--shared"); if (Args.hasArg(options::OPT_static)) CmdArgs.push_back("-Bstatic"); - else { - if (Args.hasArg(options::OPT_mdll)) - CmdArgs.push_back("--dll"); - else if (Args.hasArg(options::OPT_shared)) - CmdArgs.push_back("--shared"); + else CmdArgs.push_back("-Bdynamic"); - if (Args.hasArg(options::OPT_mdll) || Args.hasArg(options::OPT_shared)) { - CmdArgs.push_back("-e"); - if (TC.getArch() == llvm::Triple::x86) - CmdArgs.push_back("_DllMainCRTStartup@12"); - else - CmdArgs.push_back("DllMainCRTStartup"); - CmdArgs.push_back("--enable-auto-image-base"); - } + if (Args.hasArg(options::OPT_mdll) || Args.hasArg(options::OPT_shared)) { + CmdArgs.push_back("-e"); + if (TC.getArch() == llvm::Triple::x86) + CmdArgs.push_back("_DllMainCRTStartup@12"); + else + CmdArgs.push_back("DllMainCRTStartup"); + CmdArgs.push_back("--enable-auto-image-base"); } CmdArgs.push_back("-o"); Modified: vendor/clang/dist-release_60/lib/Frontend/ASTUnit.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Frontend/ASTUnit.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Frontend/ASTUnit.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -1259,6 +1259,7 @@ ASTUnit::getMainBufferWithPrecompiledPreamble( Preamble.reset(); PreambleDiagnostics.clear(); TopLevelDeclsInPreamble.clear(); + PreambleSrcLocCache.clear(); PreambleRebuildCounter = 1; } } Modified: vendor/clang/dist-release_60/lib/Frontend/CompilerInvocation.cpp ============================================================================== --- vendor/clang/dist-release_60/lib/Frontend/CompilerInvocation.cpp Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Frontend/CompilerInvocation.cpp Wed Jun 27 19:14:32 2018 (r335722) @@ -552,7 +552,7 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, Arg Args.hasFlag(OPT_ffine_grained_bitfield_accesses, OPT_fno_fine_grained_bitfield_accesses, false); Opts.DwarfDebugFlags = Args.getLastArgValue(OPT_dwarf_debug_flags); - Opts.MergeAllConstants = !Args.hasArg(OPT_fno_merge_all_constants); + Opts.MergeAllConstants = Args.hasArg(OPT_fmerge_all_constants); Opts.NoCommon = Args.hasArg(OPT_fno_common); Opts.NoImplicitFloat = Args.hasArg(OPT_no_implicit_float); Opts.OptimizeSize = getOptimizationLevelSize(Args); Modified: vendor/clang/dist-release_60/lib/Headers/avx512vlbitalgintrin.h ============================================================================== --- vendor/clang/dist-release_60/lib/Headers/avx512vlbitalgintrin.h Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Headers/avx512vlbitalgintrin.h Wed Jun 27 19:14:32 2018 (r335722) @@ -54,23 +54,23 @@ _mm256_maskz_popcnt_epi16(__mmask16 __U, __m256i __B) } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_popcnt_epi16(__m128i __A) +_mm_popcnt_epi16(__m128i __A) { return (__m128i) __builtin_ia32_vpopcntw_128((__v8hi) __A); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_popcnt_epi16(__m128i __A, __mmask8 __U, __m128i __B) +_mm_mask_popcnt_epi16(__m128i __A, __mmask8 __U, __m128i __B) { return (__m128i) __builtin_ia32_selectw_128((__mmask8) __U, - (__v8hi) _mm128_popcnt_epi16(__B), + (__v8hi) _mm_popcnt_epi16(__B), (__v8hi) __A); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_popcnt_epi16(__mmask8 __U, __m128i __B) +_mm_maskz_popcnt_epi16(__mmask8 __U, __m128i __B) { - return _mm128_mask_popcnt_epi16((__m128i) _mm_setzero_si128(), + return _mm_mask_popcnt_epi16((__m128i) _mm_setzero_si128(), __U, __B); } @@ -98,29 +98,29 @@ _mm256_maskz_popcnt_epi8(__mmask32 __U, __m256i __B) } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_popcnt_epi8(__m128i __A) +_mm_popcnt_epi8(__m128i __A) { return (__m128i) __builtin_ia32_vpopcntb_128((__v16qi) __A); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_popcnt_epi8(__m128i __A, __mmask16 __U, __m128i __B) +_mm_mask_popcnt_epi8(__m128i __A, __mmask16 __U, __m128i __B) { return (__m128i) __builtin_ia32_selectb_128((__mmask16) __U, - (__v16qi) _mm128_popcnt_epi8(__B), + (__v16qi) _mm_popcnt_epi8(__B), (__v16qi) __A); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_popcnt_epi8(__mmask16 __U, __m128i __B) +_mm_maskz_popcnt_epi8(__mmask16 __U, __m128i __B) { - return _mm128_mask_popcnt_epi8((__m128i) _mm_setzero_si128(), + return _mm_mask_popcnt_epi8((__m128i) _mm_setzero_si128(), __U, __B); } static __inline__ __mmask32 __DEFAULT_FN_ATTRS -_mm256_mask_bitshuffle_epi32_mask(__mmask32 __U, __m256i __A, __m256i __B) +_mm256_mask_bitshuffle_epi64_mask(__mmask32 __U, __m256i __A, __m256i __B) { return (__mmask32) __builtin_ia32_vpshufbitqmb256_mask((__v32qi) __A, (__v32qi) __B, @@ -128,15 +128,15 @@ _mm256_mask_bitshuffle_epi32_mask(__mmask32 __U, __m25 } static __inline__ __mmask32 __DEFAULT_FN_ATTRS -_mm256_bitshuffle_epi32_mask(__m256i __A, __m256i __B) +_mm256_bitshuffle_epi64_mask(__m256i __A, __m256i __B) { - return _mm256_mask_bitshuffle_epi32_mask((__mmask32) -1, + return _mm256_mask_bitshuffle_epi64_mask((__mmask32) -1, __A, __B); } static __inline__ __mmask16 __DEFAULT_FN_ATTRS -_mm128_mask_bitshuffle_epi16_mask(__mmask16 __U, __m128i __A, __m128i __B) +_mm_mask_bitshuffle_epi64_mask(__mmask16 __U, __m128i __A, __m128i __B) { return (__mmask16) __builtin_ia32_vpshufbitqmb128_mask((__v16qi) __A, (__v16qi) __B, @@ -144,9 +144,9 @@ _mm128_mask_bitshuffle_epi16_mask(__mmask16 __U, __m12 } static __inline__ __mmask16 __DEFAULT_FN_ATTRS -_mm128_bitshuffle_epi16_mask(__m128i __A, __m128i __B) +_mm_bitshuffle_epi64_mask(__m128i __A, __m128i __B) { - return _mm128_mask_bitshuffle_epi16_mask((__mmask16) -1, + return _mm_mask_bitshuffle_epi64_mask((__mmask16) -1, __A, __B); } Modified: vendor/clang/dist-release_60/lib/Headers/avx512vlvbmi2intrin.h ============================================================================== --- vendor/clang/dist-release_60/lib/Headers/avx512vlvbmi2intrin.h Wed Jun 27 19:14:21 2018 (r335721) +++ vendor/clang/dist-release_60/lib/Headers/avx512vlvbmi2intrin.h Wed Jun 27 19:14:32 2018 (r335722) @@ -31,13 +31,8 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512vbmi2"))) -static __inline __m128i __DEFAULT_FN_ATTRS -_mm128_setzero_hi(void) { - return (__m128i)(__v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }; -} - static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_compress_epi16(__m128i __S, __mmask8 __U, __m128i __D) +_mm_mask_compress_epi16(__m128i __S, __mmask8 __U, __m128i __D) { return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D, (__v8hi) __S, @@ -45,15 +40,15 @@ _mm128_mask_compress_epi16(__m128i __S, __mmask8 __U, } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_compress_epi16(__mmask8 __U, __m128i __D) +_mm_maskz_compress_epi16(__mmask8 __U, __m128i __D) { return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D, - (__v8hi) _mm128_setzero_hi(), + (__v8hi) _mm_setzero_si128(), __U); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_compress_epi8(__m128i __S, __mmask16 __U, __m128i __D) +_mm_mask_compress_epi8(__m128i __S, __mmask16 __U, __m128i __D) { return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D, (__v16qi) __S, @@ -61,29 +56,29 @@ _mm128_mask_compress_epi8(__m128i __S, __mmask16 __U, } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_compress_epi8(__mmask16 __U, __m128i __D) +_mm_maskz_compress_epi8(__mmask16 __U, __m128i __D) { return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D, - (__v16qi) _mm128_setzero_hi(), + (__v16qi) _mm_setzero_si128(), __U); } static __inline__ void __DEFAULT_FN_ATTRS -_mm128_mask_compressstoreu_epi16(void *__P, __mmask8 __U, __m128i __D) +_mm_mask_compressstoreu_epi16(void *__P, __mmask8 __U, __m128i __D) { __builtin_ia32_compressstorehi128_mask ((__v8hi *) __P, (__v8hi) __D, __U); } static __inline__ void __DEFAULT_FN_ATTRS -_mm128_mask_compressstoreu_epi8(void *__P, __mmask16 __U, __m128i __D) +_mm_mask_compressstoreu_epi8(void *__P, __mmask16 __U, __m128i __D) { __builtin_ia32_compressstoreqi128_mask ((__v16qi *) __P, (__v16qi) __D, __U); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_expand_epi16(__m128i __S, __mmask8 __U, __m128i __D) +_mm_mask_expand_epi16(__m128i __S, __mmask8 __U, __m128i __D) { return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D, (__v8hi) __S, @@ -91,15 +86,15 @@ _mm128_mask_expand_epi16(__m128i __S, __mmask8 __U, __ } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_expand_epi16(__mmask8 __U, __m128i __D) +_mm_maskz_expand_epi16(__mmask8 __U, __m128i __D) { return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D, - (__v8hi) _mm128_setzero_hi(), + (__v8hi) _mm_setzero_si128(), __U); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_expand_epi8(__m128i __S, __mmask16 __U, __m128i __D) +_mm_mask_expand_epi8(__m128i __S, __mmask16 __U, __m128i __D) { return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D, (__v16qi) __S, @@ -107,15 +102,15 @@ _mm128_mask_expand_epi8(__m128i __S, __mmask16 __U, __ } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_expand_epi8(__mmask16 __U, __m128i __D) +_mm_maskz_expand_epi8(__mmask16 __U, __m128i __D) { return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D, - (__v16qi) _mm128_setzero_hi(), + (__v16qi) _mm_setzero_si128(), __U); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_expandloadu_epi16(__m128i __S, __mmask8 __U, void const *__P) +_mm_mask_expandloadu_epi16(__m128i __S, __mmask8 __U, void const *__P) { return (__m128i) __builtin_ia32_expandloadhi128_mask ((const __v8hi *)__P, (__v8hi) __S, @@ -123,15 +118,15 @@ _mm128_mask_expandloadu_epi16(__m128i __S, __mmask8 __ } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_expandloadu_epi16(__mmask8 __U, void const *__P) +_mm_maskz_expandloadu_epi16(__mmask8 __U, void const *__P) { return (__m128i) __builtin_ia32_expandloadhi128_mask ((const __v8hi *)__P, - (__v8hi) _mm128_setzero_hi(), + (__v8hi) _mm_setzero_si128(), __U); } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_mask_expandloadu_epi8(__m128i __S, __mmask16 __U, void const *__P) +_mm_mask_expandloadu_epi8(__m128i __S, __mmask16 __U, void const *__P) { return (__m128i) __builtin_ia32_expandloadqi128_mask ((const __v16qi *)__P, (__v16qi) __S, @@ -139,19 +134,13 @@ _mm128_mask_expandloadu_epi8(__m128i __S, __mmask16 __ } static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm128_maskz_expandloadu_epi8(__mmask16 __U, void const *__P) +_mm_maskz_expandloadu_epi8(__mmask16 __U, void const *__P) { return (__m128i) __builtin_ia32_expandloadqi128_mask ((const __v16qi *)__P, - (__v16qi) _mm128_setzero_hi(), + (__v16qi) _mm_setzero_si128(), __U); } -static __inline __m256i __DEFAULT_FN_ATTRS -_mm256_setzero_hi(void) { - return (__m256i)(__v16hi){ 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }; -} - static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_mask_compress_epi16(__m256i __S, __mmask16 __U, __m256i __D) { @@ -164,7 +153,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_maskz_compress_epi16(__mmask16 __U, __m256i __D) { return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi) __D, - (__v16hi) _mm256_setzero_hi(), + (__v16hi) _mm256_setzero_si256(), __U); } @@ -180,7 +169,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_maskz_compress_epi8(__mmask32 __U, __m256i __D) { return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi) __D, - (__v32qi) _mm256_setzero_hi(), + (__v32qi) _mm256_setzero_si256(), __U); } @@ -210,7 +199,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_maskz_expand_epi16(__mmask16 __U, __m256i __D) { return (__m256i) __builtin_ia32_expandhi256_mask ((__v16hi) __D, - (__v16hi) _mm256_setzero_hi(), + (__v16hi) _mm256_setzero_si256(), __U); } @@ -226,7 +215,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_maskz_expand_epi8(__mmask32 __U, __m256i __D) { return (__m256i) __builtin_ia32_expandqi256_mask ((__v32qi) __D, - (__v32qi) _mm256_setzero_hi(), + (__v32qi) _mm256_setzero_si256(), __U); } @@ -242,7 +231,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_maskz_expandloadu_epi16(__mmask16 __U, void const *__P) { return (__m256i) __builtin_ia32_expandloadhi256_mask ((const __v16hi *)__P, - (__v16hi) _mm256_setzero_hi(), + (__v16hi) _mm256_setzero_si256(), __U); } @@ -258,7 +247,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_maskz_expandloadu_epi8(__mmask32 __U, void const *__P) { return (__m256i) __builtin_ia32_expandloadqi256_mask ((const __v32qi *)__P, - (__v32qi) _mm256_setzero_hi(), + (__v32qi) _mm256_setzero_si256(), __U); } @@ -270,23 +259,23 @@ _mm256_maskz_expandloadu_epi8(__mmask32 __U, void cons (__mmask8)(U)); }) #define _mm256_maskz_shldi_epi64(U, A, B, I) \ - _mm256_mask_shldi_epi64(_mm256_setzero_hi(), (U), (A), (B), (I)) + _mm256_mask_shldi_epi64(_mm256_setzero_si256(), (U), (A), (B), (I)) #define _mm256_shldi_epi64(A, B, I) \ _mm256_mask_shldi_epi64(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I)) -#define _mm128_mask_shldi_epi64(S, U, A, B, I) __extension__ ({ \ +#define _mm_mask_shldi_epi64(S, U, A, B, I) __extension__ ({ \ (__m128i)__builtin_ia32_vpshldq128_mask((__v2di)(A), \ (__v2di)(B), \ (int)(I), \ (__v2di)(S), \ (__mmask8)(U)); }) -#define _mm128_maskz_shldi_epi64(U, A, B, I) \ - _mm128_mask_shldi_epi64(_mm128_setzero_hi(), (U), (A), (B), (I)) +#define _mm_maskz_shldi_epi64(U, A, B, I) \ + _mm_mask_shldi_epi64(_mm_setzero_si128(), (U), (A), (B), (I)) -#define _mm128_shldi_epi64(A, B, I) \ - _mm128_mask_shldi_epi64(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) +#define _mm_shldi_epi64(A, B, I) \ + _mm_mask_shldi_epi64(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) #define _mm256_mask_shldi_epi32(S, U, A, B, I) __extension__ ({ \ (__m256i)__builtin_ia32_vpshldd256_mask((__v8si)(A), \ @@ -296,23 +285,23 @@ _mm256_maskz_expandloadu_epi8(__mmask32 __U, void cons (__mmask8)(U)); }) #define _mm256_maskz_shldi_epi32(U, A, B, I) \ - _mm256_mask_shldi_epi32(_mm256_setzero_hi(), (U), (A), (B), (I)) + _mm256_mask_shldi_epi32(_mm256_setzero_si256(), (U), (A), (B), (I)) #define _mm256_shldi_epi32(A, B, I) \ _mm256_mask_shldi_epi32(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I)) -#define _mm128_mask_shldi_epi32(S, U, A, B, I) __extension__ ({ \ +#define _mm_mask_shldi_epi32(S, U, A, B, I) __extension__ ({ \ (__m128i)__builtin_ia32_vpshldd128_mask((__v4si)(A), \ (__v4si)(B), \ (int)(I), \ (__v4si)(S), \ (__mmask8)(U)); }) -#define _mm128_maskz_shldi_epi32(U, A, B, I) \ - _mm128_mask_shldi_epi32(_mm128_setzero_hi(), (U), (A), (B), (I)) +#define _mm_maskz_shldi_epi32(U, A, B, I) \ + _mm_mask_shldi_epi32(_mm_setzero_si128(), (U), (A), (B), (I)) -#define _mm128_shldi_epi32(A, B, I) \ - _mm128_mask_shldi_epi32(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) +#define _mm_shldi_epi32(A, B, I) \ + _mm_mask_shldi_epi32(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) #define _mm256_mask_shldi_epi16(S, U, A, B, I) __extension__ ({ \ (__m256i)__builtin_ia32_vpshldw256_mask((__v16hi)(A), \ @@ -322,23 +311,23 @@ _mm256_maskz_expandloadu_epi8(__mmask32 __U, void cons (__mmask16)(U)); }) #define _mm256_maskz_shldi_epi16(U, A, B, I) \ - _mm256_mask_shldi_epi16(_mm256_setzero_hi(), (U), (A), (B), (I)) + _mm256_mask_shldi_epi16(_mm256_setzero_si256(), (U), (A), (B), (I)) #define _mm256_shldi_epi16(A, B, I) \ _mm256_mask_shldi_epi16(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I)) -#define _mm128_mask_shldi_epi16(S, U, A, B, I) __extension__ ({ \ +#define _mm_mask_shldi_epi16(S, U, A, B, I) __extension__ ({ \ (__m128i)__builtin_ia32_vpshldw128_mask((__v8hi)(A), \ (__v8hi)(B), \ (int)(I), \ (__v8hi)(S), \ (__mmask8)(U)); }) -#define _mm128_maskz_shldi_epi16(U, A, B, I) \ - _mm128_mask_shldi_epi16(_mm128_setzero_hi(), (U), (A), (B), (I)) +#define _mm_maskz_shldi_epi16(U, A, B, I) \ + _mm_mask_shldi_epi16(_mm_setzero_si128(), (U), (A), (B), (I)) -#define _mm128_shldi_epi16(A, B, I) \ - _mm128_mask_shldi_epi16(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) +#define _mm_shldi_epi16(A, B, I) \ + _mm_mask_shldi_epi16(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) #define _mm256_mask_shrdi_epi64(S, U, A, B, I) __extension__ ({ \ (__m256i)__builtin_ia32_vpshrdq256_mask((__v4di)(A), \ @@ -348,23 +337,23 @@ _mm256_maskz_expandloadu_epi8(__mmask32 __U, void cons (__mmask8)(U)); }) #define _mm256_maskz_shrdi_epi64(U, A, B, I) \ - _mm256_mask_shrdi_epi64(_mm256_setzero_hi(), (U), (A), (B), (I)) + _mm256_mask_shrdi_epi64(_mm256_setzero_si256(), (U), (A), (B), (I)) #define _mm256_shrdi_epi64(A, B, I) \ _mm256_mask_shrdi_epi64(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I)) -#define _mm128_mask_shrdi_epi64(S, U, A, B, I) __extension__ ({ \ +#define _mm_mask_shrdi_epi64(S, U, A, B, I) __extension__ ({ \ (__m128i)__builtin_ia32_vpshrdq128_mask((__v2di)(A), \ (__v2di)(B), \ (int)(I), \ (__v2di)(S), \ (__mmask8)(U)); }) -#define _mm128_maskz_shrdi_epi64(U, A, B, I) \ - _mm128_mask_shrdi_epi64(_mm128_setzero_hi(), (U), (A), (B), (I)) +#define _mm_maskz_shrdi_epi64(U, A, B, I) \ + _mm_mask_shrdi_epi64(_mm_setzero_si128(), (U), (A), (B), (I)) -#define _mm128_shrdi_epi64(A, B, I) \ - _mm128_mask_shrdi_epi64(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) +#define _mm_shrdi_epi64(A, B, I) \ + _mm_mask_shrdi_epi64(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I)) #define _mm256_mask_shrdi_epi32(S, U, A, B, I) __extension__ ({ \ (__m256i)__builtin_ia32_vpshrdd256_mask((__v8si)(A), \ @@ -374,23 +363,23 @@ _mm256_maskz_expandloadu_epi8(__mmask32 __U, void cons (__mmask8)(U)); }) #define _mm256_maskz_shrdi_epi32(U, A, B, I) \ - _mm256_mask_shrdi_epi32(_mm256_setzero_hi(), (U), (A), (B), (I)) + _mm256_mask_shrdi_epi32(_mm256_setzero_si256(), (U), (A), (B), (I)) #define _mm256_shrdi_epi32(A, B, I) \ _mm256_mask_shrdi_epi32(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I)) -#define _mm128_mask_shrdi_epi32(S, U, A, B, I) __extension__ ({ \ +#define _mm_mask_shrdi_epi32(S, U, A, B, I) __extension__ ({ \ (__m128i)__builtin_ia32_vpshrdd128_mask((__v4si)(A), \ (__v4si)(B), \ (int)(I), \ (__v4si)(S), \ (__mmask8)(U)); }) -#define _mm128_maskz_shrdi_epi32(U, A, B, I) \ - _mm128_mask_shrdi_epi32(_mm128_setzero_hi(), (U), (A), (B), (I)) +#define _mm_maskz_shrdi_epi32(U, A, B, I) \ *** DIFF OUTPUT TRUNCATED AT 1000 LINES *** From owner-svn-src-vendor@freebsd.org Wed Jun 27 19:14:41 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 7795E1002F83; Wed, 27 Jun 2018 19:14:41 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 26F298DBC9; Wed, 27 Jun 2018 19:14:41 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id E38CD272FC; Wed, 27 Jun 2018 19:14:40 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5RJEe4A042994; Wed, 27 Jun 2018 19:14:40 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5RJEeRM042993; Wed, 27 Jun 2018 19:14:40 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201806271914.w5RJEeRM042993@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 27 Jun 2018 19:14:40 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335723 - vendor/clang/clang-release_601-r335540 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/clang/clang-release_601-r335540 X-SVN-Commit-Revision: 335723 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jun 2018 19:14:41 -0000 Author: dim Date: Wed Jun 27 19:14:40 2018 New Revision: 335723 URL: https://svnweb.freebsd.org/changeset/base/335723 Log: Tag clang 6.0.1 release r335540. Added: vendor/clang/clang-release_601-r335540/ - copied from r335722, vendor/clang/dist-release_60/ From owner-svn-src-vendor@freebsd.org Wed Jun 27 19:14:47 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 581CB1003004; Wed, 27 Jun 2018 19:14:47 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 929958DCB1; Wed, 27 Jun 2018 19:14:45 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 2FD0C272FD; Wed, 27 Jun 2018 19:14:45 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5RJEjaR043044; Wed, 27 Jun 2018 19:14:45 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5RJEjXR043043; Wed, 27 Jun 2018 19:14:45 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201806271914.w5RJEjXR043043@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 27 Jun 2018 19:14:45 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335724 - vendor/compiler-rt/dist-release_60/lib/sanitizer_common X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/compiler-rt/dist-release_60/lib/sanitizer_common X-SVN-Commit-Revision: 335724 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jun 2018 19:14:47 -0000 Author: dim Date: Wed Jun 27 19:14:44 2018 New Revision: 335724 URL: https://svnweb.freebsd.org/changeset/base/335724 Log: Vendor import of compiler-rt 6.0.1 release r335540: https://llvm.org/svn/llvm-project/compiler-rt/tags/RELEASE_601/final@335540 Modified: vendor/compiler-rt/dist-release_60/lib/sanitizer_common/sanitizer_platform_limits_posix.cc Modified: vendor/compiler-rt/dist-release_60/lib/sanitizer_common/sanitizer_platform_limits_posix.cc ============================================================================== --- vendor/compiler-rt/dist-release_60/lib/sanitizer_common/sanitizer_platform_limits_posix.cc Wed Jun 27 19:14:40 2018 (r335723) +++ vendor/compiler-rt/dist-release_60/lib/sanitizer_common/sanitizer_platform_limits_posix.cc Wed Jun 27 19:14:44 2018 (r335724) @@ -159,7 +159,6 @@ typedef struct user_fpregs elf_fpregset_t; # include #endif #include -#include #include #include #include @@ -253,7 +252,19 @@ namespace __sanitizer { #endif // SANITIZER_LINUX || SANITIZER_FREEBSD #if SANITIZER_LINUX && !SANITIZER_ANDROID - unsigned struct_ustat_sz = sizeof(struct ustat); + // Use pre-computed size of struct ustat to avoid which + // has been removed from glibc 2.28. +#if defined(__aarch64__) || defined(__s390x__) || defined (__mips64) \ + || defined(__powerpc64__) || defined(__arch64__) || defined(__sparcv9) \ + || defined(__x86_64__) +#define SIZEOF_STRUCT_USTAT 32 +#elif defined(__arm__) || defined(__i386__) || defined(__mips__) \ + || defined(__powerpc__) || defined(__s390__) +#define SIZEOF_STRUCT_USTAT 20 +#else +#error Unknown size of struct ustat +#endif + unsigned struct_ustat_sz = SIZEOF_STRUCT_USTAT; unsigned struct_rlimit64_sz = sizeof(struct rlimit64); unsigned struct_statvfs64_sz = sizeof(struct statvfs64); #endif // SANITIZER_LINUX && !SANITIZER_ANDROID From owner-svn-src-vendor@freebsd.org Wed Jun 27 19:14:51 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id D4DE01003050; Wed, 27 Jun 2018 19:14:51 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4671F8DD41; Wed, 27 Jun 2018 19:14:48 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 8A993272FE; Wed, 27 Jun 2018 19:14:48 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5RJEm2g043090; Wed, 27 Jun 2018 19:14:48 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5RJEmYs043089; Wed, 27 Jun 2018 19:14:48 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201806271914.w5RJEmYs043089@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 27 Jun 2018 19:14:48 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335725 - vendor/compiler-rt/compiler-rt-release_601-r335540 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/compiler-rt/compiler-rt-release_601-r335540 X-SVN-Commit-Revision: 335725 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jun 2018 19:14:52 -0000 Author: dim Date: Wed Jun 27 19:14:48 2018 New Revision: 335725 URL: https://svnweb.freebsd.org/changeset/base/335725 Log: Tag compiler-rt 6.0.1 release r335540. Added: vendor/compiler-rt/compiler-rt-release_601-r335540/ - copied from r335724, vendor/compiler-rt/dist-release_60/ From owner-svn-src-vendor@freebsd.org Wed Jun 27 19:14:58 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 3489D1003085; Wed, 27 Jun 2018 19:14:58 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 5876C8DE8F; Wed, 27 Jun 2018 19:14:56 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 01604272FF; Wed, 27 Jun 2018 19:14:56 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5RJEt6I043145; Wed, 27 Jun 2018 19:14:55 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5RJEtSk043140; Wed, 27 Jun 2018 19:14:55 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201806271914.w5RJEtSk043140@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 27 Jun 2018 19:14:55 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335726 - in vendor/libc++/dist-release_60: include src/support/runtime test/libcxx/debug/containers test/std/language.support/support.exception/uncaught X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in vendor/libc++/dist-release_60: include src/support/runtime test/libcxx/debug/containers test/std/language.support/support.exception/uncaught X-SVN-Commit-Revision: 335726 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jun 2018 19:14:58 -0000 Author: dim Date: Wed Jun 27 19:14:54 2018 New Revision: 335726 URL: https://svnweb.freebsd.org/changeset/base/335726 Log: Vendor import of libc++ 6.0.1 release r335540: https://llvm.org/svn/llvm-project/libcxx/tags/RELEASE_601/final@335540 Modified: vendor/libc++/dist-release_60/include/list vendor/libc++/dist-release_60/src/support/runtime/exception_libcxxabi.ipp vendor/libc++/dist-release_60/test/libcxx/debug/containers/db_sequence_container_iterators.pass.cpp vendor/libc++/dist-release_60/test/std/language.support/support.exception/uncaught/uncaught_exceptions.pass.cpp Modified: vendor/libc++/dist-release_60/include/list ============================================================================== --- vendor/libc++/dist-release_60/include/list Wed Jun 27 19:14:48 2018 (r335725) +++ vendor/libc++/dist-release_60/include/list Wed Jun 27 19:14:54 2018 (r335726) @@ -2058,15 +2058,15 @@ list<_Tp, _Alloc>::splice(const_iterator __p, list& __ #endif if (__f != __l) { + __link_pointer __first = __f.__ptr_; + --__l; + __link_pointer __last = __l.__ptr_; if (this != &__c) { - size_type __s = _VSTD::distance(__f, __l); + size_type __s = _VSTD::distance(__f, __l) + 1; __c.__sz() -= __s; base::__sz() += __s; } - __link_pointer __first = __f.__ptr_; - --__l; - __link_pointer __last = __l.__ptr_; base::__unlink_nodes(__first, __last); __link_nodes(__p.__ptr_, __first, __last); #if _LIBCPP_DEBUG_LEVEL >= 2 Modified: vendor/libc++/dist-release_60/src/support/runtime/exception_libcxxabi.ipp ============================================================================== --- vendor/libc++/dist-release_60/src/support/runtime/exception_libcxxabi.ipp Wed Jun 27 19:14:48 2018 (r335725) +++ vendor/libc++/dist-release_60/src/support/runtime/exception_libcxxabi.ipp Wed Jun 27 19:14:54 2018 (r335726) @@ -18,7 +18,7 @@ bool uncaught_exception() _NOEXCEPT { return uncaught_ int uncaught_exceptions() _NOEXCEPT { -# if _LIBCPPABI_VERSION > 1101 +# if _LIBCPPABI_VERSION > 1001 return __cxa_uncaught_exceptions(); # else return __cxa_uncaught_exception() ? 1 : 0; Modified: vendor/libc++/dist-release_60/test/libcxx/debug/containers/db_sequence_container_iterators.pass.cpp ============================================================================== --- vendor/libc++/dist-release_60/test/libcxx/debug/containers/db_sequence_container_iterators.pass.cpp Wed Jun 27 19:14:48 2018 (r335725) +++ vendor/libc++/dist-release_60/test/libcxx/debug/containers/db_sequence_container_iterators.pass.cpp Wed Jun 27 19:14:54 2018 (r335726) @@ -42,6 +42,7 @@ struct SequenceContainerChecks : BasicContainerChecks< Base::run(); try { FrontOnEmptyContainer(); + if constexpr (CT != CT_ForwardList) { AssignInvalidates(); BackOnEmptyContainer(); @@ -50,6 +51,8 @@ struct SequenceContainerChecks : BasicContainerChecks< InsertIterIterIter(); EmplaceIterValue(); EraseIterIter(); + } else { + SpliceFirstElemAfter(); } if constexpr (CT == CT_Vector || CT == CT_Deque || CT == CT_List) { PopBack(); @@ -57,12 +60,66 @@ struct SequenceContainerChecks : BasicContainerChecks< if constexpr (CT == CT_List || CT == CT_Deque) { PopFront(); // FIXME: Run with forward list as well } + if constexpr (CT == CT_List || CT == CT_ForwardList) { + RemoveFirstElem(); + } + if constexpr (CT == CT_List) { + SpliceFirstElem(); + } } catch (...) { assert(false && "uncaught debug exception"); } } private: + static void RemoveFirstElem() { + // See llvm.org/PR35564 + CHECKPOINT("remove()"); + { + Container C = makeContainer(1); + auto FirstVal = *(C.begin()); + C.remove(FirstVal); + assert(C.empty()); + } + { + Container C = {1, 1, 1, 1}; + auto FirstVal = *(C.begin()); + C.remove(FirstVal); + assert(C.empty()); + } + } + + static void SpliceFirstElem() { + // See llvm.org/PR35564 + CHECKPOINT("splice()"); + { + Container C = makeContainer(1); + Container C2; + C2.splice(C2.end(), C, C.begin(), ++C.begin()); + } + { + Container C = makeContainer(1); + Container C2; + C2.splice(C2.end(), C, C.begin()); + } + } + + + static void SpliceFirstElemAfter() { + // See llvm.org/PR35564 + CHECKPOINT("splice()"); + { + Container C = makeContainer(1); + Container C2; + C2.splice_after(C2.begin(), C, C.begin(), ++C.begin()); + } + { + Container C = makeContainer(1); + Container C2; + C2.splice_after(C2.begin(), C, C.begin()); + } + } + static void AssignInvalidates() { CHECKPOINT("assign(Size, Value)"); Container C(allocator_type{}); Modified: vendor/libc++/dist-release_60/test/std/language.support/support.exception/uncaught/uncaught_exceptions.pass.cpp ============================================================================== --- vendor/libc++/dist-release_60/test/std/language.support/support.exception/uncaught/uncaught_exceptions.pass.cpp Wed Jun 27 19:14:48 2018 (r335725) +++ vendor/libc++/dist-release_60/test/std/language.support/support.exception/uncaught/uncaught_exceptions.pass.cpp Wed Jun 27 19:14:54 2018 (r335726) @@ -15,40 +15,48 @@ // XFAIL: availability=macosx10.9 // XFAIL: availability=macosx10.10 // XFAIL: availability=macosx10.11 +// XFAIL: with_system_cxx_lib=macosx10.12 +// XFAIL: with_system_cxx_lib=macosx10.13 // test uncaught_exceptions #include #include -struct A -{ - ~A() - { - assert(std::uncaught_exceptions() > 0); - } -}; +struct Uncaught { + Uncaught(int depth) : d_(depth) {} + ~Uncaught() { assert(std::uncaught_exceptions() == d_); } + int d_; + }; -struct B -{ - B() - { - // http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_defects.html#475 - assert(std::uncaught_exceptions() == 0); +struct Outer { + Outer(int depth) : d_(depth) {} + ~Outer() { + try { + assert(std::uncaught_exceptions() == d_); + Uncaught u(d_+1); + throw 2; } + catch (int) {} + } + int d_; }; -int main() -{ - try +int main () { + assert(std::uncaught_exceptions() == 0); { - A a; - assert(std::uncaught_exceptions() == 0); - throw B(); + Outer o(0); } - catch (...) + + assert(std::uncaught_exceptions() == 0); { - assert(std::uncaught_exception() == 0); + try { + Outer o(1); + throw 1; + } + catch (int) { + assert(std::uncaught_exceptions() == 0); + } } assert(std::uncaught_exceptions() == 0); } From owner-svn-src-vendor@freebsd.org Wed Jun 27 19:15:06 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 7BCF010030D6; Wed, 27 Jun 2018 19:15:06 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 83D568DF89; Wed, 27 Jun 2018 19:15:05 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 64C7927301; Wed, 27 Jun 2018 19:15:05 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5RJF5dV043266; Wed, 27 Jun 2018 19:15:05 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5RJF2UH043254; Wed, 27 Jun 2018 19:15:02 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201806271915.w5RJF2UH043254@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 27 Jun 2018 19:15:02 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335728 - in vendor/lld/dist-release_60: COFF ELF ELF/Arch MinGW test/COFF test/ELF test/MinGW X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in vendor/lld/dist-release_60: COFF ELF ELF/Arch MinGW test/COFF test/ELF test/MinGW X-SVN-Commit-Revision: 335728 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jun 2018 19:15:06 -0000 Author: dim Date: Wed Jun 27 19:15:02 2018 New Revision: 335728 URL: https://svnweb.freebsd.org/changeset/base/335728 Log: Vendor import of lld 6.0.1 release r335540: https://llvm.org/svn/llvm-project/lld/tags/RELEASE_601/final@335540 Modified: vendor/lld/dist-release_60/COFF/Config.h vendor/lld/dist-release_60/COFF/Driver.cpp vendor/lld/dist-release_60/COFF/DriverUtils.cpp vendor/lld/dist-release_60/COFF/Options.td vendor/lld/dist-release_60/ELF/Arch/Mips.cpp vendor/lld/dist-release_60/ELF/Config.h vendor/lld/dist-release_60/ELF/Driver.cpp vendor/lld/dist-release_60/MinGW/Driver.cpp vendor/lld/dist-release_60/MinGW/Options.td vendor/lld/dist-release_60/test/COFF/def-export-stdcall.s vendor/lld/dist-release_60/test/ELF/mips-26-n32-n64.s vendor/lld/dist-release_60/test/ELF/mips-plt-r6.s vendor/lld/dist-release_60/test/MinGW/driver.test Modified: vendor/lld/dist-release_60/COFF/Config.h ============================================================================== --- vendor/lld/dist-release_60/COFF/Config.h Wed Jun 27 19:14:58 2018 (r335727) +++ vendor/lld/dist-release_60/COFF/Config.h Wed Jun 27 19:15:02 2018 (r335728) @@ -175,6 +175,7 @@ struct Configuration { bool AppContainer = false; bool MinGW = false; bool WarnLocallyDefinedImported = true; + bool KillAt = false; }; extern Configuration *Config; Modified: vendor/lld/dist-release_60/COFF/Driver.cpp ============================================================================== --- vendor/lld/dist-release_60/COFF/Driver.cpp Wed Jun 27 19:14:58 2018 (r335727) +++ vendor/lld/dist-release_60/COFF/Driver.cpp Wed Jun 27 19:15:02 2018 (r335728) @@ -970,6 +970,10 @@ void LinkerDriver::link(ArrayRef ArgsArr if (Args.hasArg(OPT_lldsavetemps)) Config->SaveTemps = true; + // Handle /kill-at + if (Args.hasArg(OPT_kill_at)) + Config->KillAt = true; + // Handle /lldltocache if (auto *Arg = Args.getLastArg(OPT_lldltocache)) Config->LTOCache = Arg->getValue(); Modified: vendor/lld/dist-release_60/COFF/DriverUtils.cpp ============================================================================== --- vendor/lld/dist-release_60/COFF/DriverUtils.cpp Wed Jun 27 19:14:58 2018 (r335727) +++ vendor/lld/dist-release_60/COFF/DriverUtils.cpp Wed Jun 27 19:15:02 2018 (r335728) @@ -561,6 +561,26 @@ static StringRef undecorate(StringRef Sym) { return Sym.startswith("_") ? Sym.substr(1) : Sym; } +// Convert stdcall/fastcall style symbols into unsuffixed symbols, +// with or without a leading underscore. (MinGW specific.) +static StringRef killAt(StringRef Sym, bool Prefix) { + if (Sym.empty()) + return Sym; + // Strip any trailing stdcall suffix + Sym = Sym.substr(0, Sym.find('@', 1)); + if (!Sym.startswith("@")) { + if (Prefix && !Sym.startswith("_")) + return Saver.save("_" + Sym); + return Sym; + } + // For fastcall, remove the leading @ and replace it with an + // underscore, if prefixes are used. + Sym = Sym.substr(1); + if (Prefix) + Sym = Saver.save("_" + Sym); + return Sym; +} + // Performs error checking on all /export arguments. // It also sets ordinals. void fixupExports() { @@ -590,6 +610,15 @@ void fixupExports() { E.ExportName = undecorate(E.Name); } else { E.ExportName = undecorate(E.ExtName.empty() ? E.Name : E.ExtName); + } + } + + if (Config->KillAt && Config->Machine == I386) { + for (Export &E : Config->Exports) { + E.Name = killAt(E.Name, true); + E.ExportName = killAt(E.ExportName, false); + E.ExtName = killAt(E.ExtName, true); + E.SymbolName = killAt(E.SymbolName, true); } } Modified: vendor/lld/dist-release_60/COFF/Options.td ============================================================================== --- vendor/lld/dist-release_60/COFF/Options.td Wed Jun 27 19:14:58 2018 (r335727) +++ vendor/lld/dist-release_60/COFF/Options.td Wed Jun 27 19:15:02 2018 (r335728) @@ -121,6 +121,7 @@ def help_q : Flag<["/?", "-?"], "">, Alias; def debug_ghash : F<"debug:ghash">; def debug_dwarf : F<"debug:dwarf">; def export_all_symbols : F<"export-all-symbols">; +def kill_at : F<"kill-at">; def lldmingw : F<"lldmingw">; def msvclto : F<"msvclto">; def output_def : Joined<["/", "-"], "output-def:">; Modified: vendor/lld/dist-release_60/ELF/Arch/Mips.cpp ============================================================================== --- vendor/lld/dist-release_60/ELF/Arch/Mips.cpp Wed Jun 27 19:14:58 2018 (r335727) +++ vendor/lld/dist-release_60/ELF/Arch/Mips.cpp Wed Jun 27 19:15:02 2018 (r335728) @@ -296,7 +296,8 @@ template void MIPS::writePltHeader( write32(Buf + 20, 0x0018c082); // srl $24, $24, 2 } - write32(Buf + 24, 0x0320f809); // jalr $25 + uint32_t JalrInst = Config->ZHazardplt ? 0x0320fc09 : 0x0320f809; + write32(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25 write32(Buf + 28, 0x2718fffe); // subu $24, $24, 2 uint64_t GotPlt = InX::GotPlt->getVA(); @@ -330,9 +331,12 @@ void MIPS::writePlt(uint8_t *Buf, uint64_t GotPl return; } + uint32_t JrInst = isMipsR6() ? (Config->ZHazardplt ? 0x03200409 : 0x03200009) + : (Config->ZHazardplt ? 0x03200408 : 0x03200008); + write32(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) write32(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) - write32(Buf + 8, isMipsR6() ? 0x03200009 : 0x03200008); // jr $25 + write32(Buf + 8, JrInst); // jr $25 / jr.hb $25 write32(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) writeRelocation(Buf, GotPltEntryAddr + 0x8000, 16, 16); writeRelocation(Buf + 4, GotPltEntryAddr, 16, 0); Modified: vendor/lld/dist-release_60/ELF/Config.h ============================================================================== --- vendor/lld/dist-release_60/ELF/Config.h Wed Jun 27 19:14:58 2018 (r335727) +++ vendor/lld/dist-release_60/ELF/Config.h Wed Jun 27 19:15:02 2018 (r335728) @@ -151,6 +151,7 @@ struct Configuration { bool WarnMissingEntry; bool ZCombreloc; bool ZExecstack; + bool ZHazardplt; bool ZNocopyreloc; bool ZNodelete; bool ZNodlopen; Modified: vendor/lld/dist-release_60/ELF/Driver.cpp ============================================================================== --- vendor/lld/dist-release_60/ELF/Driver.cpp Wed Jun 27 19:14:58 2018 (r335727) +++ vendor/lld/dist-release_60/ELF/Driver.cpp Wed Jun 27 19:15:02 2018 (r335728) @@ -668,6 +668,7 @@ void LinkerDriver::readConfigs(opt::InputArgList &Args Config->WarnCommon = Args.hasArg(OPT_warn_common); Config->ZCombreloc = !hasZOption(Args, "nocombreloc"); Config->ZExecstack = hasZOption(Args, "execstack"); + Config->ZHazardplt = hasZOption(Args, "hazardplt"); Config->ZNocopyreloc = hasZOption(Args, "nocopyreloc"); Config->ZNodelete = hasZOption(Args, "nodelete"); Config->ZNodlopen = hasZOption(Args, "nodlopen"); Modified: vendor/lld/dist-release_60/MinGW/Driver.cpp ============================================================================== --- vendor/lld/dist-release_60/MinGW/Driver.cpp Wed Jun 27 19:14:58 2018 (r335727) +++ vendor/lld/dist-release_60/MinGW/Driver.cpp Wed Jun 27 19:15:02 2018 (r335728) @@ -154,6 +154,8 @@ bool mingw::link(ArrayRef ArgsArr, raw_o Add("-debug:dwarf"); if (Args.hasArg(OPT_large_address_aware)) Add("-largeaddressaware"); + if (Args.hasArg(OPT_kill_at)) + Add("-kill-at"); if (Args.getLastArgValue(OPT_m) != "thumb2pe" && Args.getLastArgValue(OPT_m) != "arm64pe" && !Args.hasArg(OPT_dynamicbase)) Modified: vendor/lld/dist-release_60/MinGW/Options.td ============================================================================== --- vendor/lld/dist-release_60/MinGW/Options.td Wed Jun 27 19:14:58 2018 (r335727) +++ vendor/lld/dist-release_60/MinGW/Options.td Wed Jun 27 19:15:02 2018 (r335728) @@ -14,6 +14,7 @@ def export_all_symbols: F<"export-all-symbols">, def gc_sections: F<"gc-sections">, HelpText<"Remove unused sections">; def icf: J<"icf=">, HelpText<"Identical code folding">; def image_base: S<"image-base">, HelpText<"Base address of the program">; +def kill_at: F<"kill-at">, HelpText<"Remove @n from exported symbols">; def l: JoinedOrSeparate<["-"], "l">, MetaVarName<"">, HelpText<"Root name of library to use">; def m: JoinedOrSeparate<["-"], "m">, HelpText<"Set target emulation">; @@ -51,6 +52,7 @@ def build_id: F<"build-id">; def disable_auto_image_base: F<"disable-auto-image-base">; def enable_auto_image_base: F<"enable-auto-image-base">; def enable_auto_import: F<"enable-auto-import">; +def end_group: J<"end-group">; def full_shutdown: Flag<["--"], "full-shutdown">; def high_entropy_va: F<"high-entropy-va">, HelpText<"Enable 64-bit ASLR">; def major_image_version: S<"major-image-version">; @@ -59,6 +61,7 @@ def no_seh: F<"no-seh">; def nxcompat: F<"nxcompat">, HelpText<"Enable data execution prevention">; def pic_executable: F<"pic-executable">; def sysroot: J<"sysroot">, HelpText<"Sysroot">; +def start_group: J<"start-group">; def tsaware: F<"tsaware">, HelpText<"Create Terminal Server aware executable">; def v: Flag<["-"], "v">, HelpText<"Display the version number">; def version: F<"version">, HelpText<"Display the version number and exit">; Modified: vendor/lld/dist-release_60/test/COFF/def-export-stdcall.s ============================================================================== --- vendor/lld/dist-release_60/test/COFF/def-export-stdcall.s Wed Jun 27 19:14:58 2018 (r335727) +++ vendor/lld/dist-release_60/test/COFF/def-export-stdcall.s Wed Jun 27 19:15:02 2018 (r335728) @@ -46,7 +46,8 @@ # DECORATED-EXPORTS: Name: vectorcall@@8 -# RUN: echo -e "LIBRARY foo\nEXPORTS\n stdcall@8\n @fastcall@8" > %t.def +# GNU tools don't support vectorcall at the moment, but test it for completeness. +# RUN: echo -e "LIBRARY foo\nEXPORTS\n stdcall@8\n @fastcall@8\n vectorcall@@8" > %t.def # RUN: lld-link -lldmingw -entry:dllmain -dll -def:%t.def %t.obj -out:%t.dll -implib:%t.lib # RUN: llvm-readobj %t.lib | FileCheck -check-prefix DECORATED-MINGW-IMPLIB %s # RUN: llvm-readobj -coff-exports %t.dll | FileCheck -check-prefix DECORATED-MINGW-EXPORTS %s @@ -57,9 +58,39 @@ # DECORATED-MINGW-IMPLIB: Name type: noprefix # DECORATED-MINGW-IMPLIB-NEXT: __imp__stdcall@8 # DECORATED-MINGW-IMPLIB-NEXT: _stdcall@8 +# GNU tools don't support vectorcall, but this test is just to track that +# lld's behaviour remains consistent over time. +# DECORATED-MINGW-IMPLIB: Name type: name +# DECORATED-MINGW-IMPLIB-NEXT: __imp_vectorcall@@8 +# DECORATED-MINGW-IMPLIB-NEXT: vectorcall@@8 # DECORATED-MINGW-EXPORTS: Name: @fastcall@8 # DECORATED-MINGW-EXPORTS: Name: stdcall@8 +# DECORATED-MINGW-EXPORTS: Name: vectorcall@@8 + +# RUN: lld-link -lldmingw -kill-at -entry:dllmain -dll -def:%t.def %t.obj -out:%t.dll -implib:%t.lib +# RUN: llvm-readobj %t.lib | FileCheck -check-prefix MINGW-KILL-AT-IMPLIB %s +# RUN: llvm-readobj -coff-exports %t.dll | FileCheck -check-prefix MINGW-KILL-AT-EXPORTS %s + +# RUN: lld-link -lldmingw -kill-at -entry:dllmain -dll %t.obj -out:%t.dll -implib:%t.lib +# RUN: llvm-readobj %t.lib | FileCheck -check-prefix MINGW-KILL-AT-IMPLIB %s +# RUN: llvm-readobj -coff-exports %t.dll | FileCheck -check-prefix MINGW-KILL-AT-EXPORTS %s + +# MINGW-KILL-AT-IMPLIB: Name type: noprefix +# MINGW-KILL-AT-IMPLIB: __imp__fastcall +# MINGW-KILL-AT-IMPLIB-NEXT: _fastcall +# MINGW-KILL-AT-IMPLIB: Name type: noprefix +# MINGW-KILL-AT-IMPLIB-NEXT: __imp__stdcall +# MINGW-KILL-AT-IMPLIB-NEXT: _stdcall +# GNU tools don't support vectorcall, but this test is just to track that +# lld's behaviour remains consistent over time. +# MINGW-KILL-AT-IMPLIB: Name type: noprefix +# MINGW-KILL-AT-IMPLIB-NEXT: __imp__vectorcall +# MINGW-KILL-AT-IMPLIB-NEXT: _vectorcall + +# MINGW-KILL-AT-EXPORTS: Name: fastcall +# MINGW-KILL-AT-EXPORTS: Name: stdcall +# MINGW-KILL-AT-EXPORTS: Name: vectorcall .def _stdcall@8; Modified: vendor/lld/dist-release_60/test/ELF/mips-26-n32-n64.s ============================================================================== --- vendor/lld/dist-release_60/test/ELF/mips-26-n32-n64.s Wed Jun 27 19:14:58 2018 (r335727) +++ vendor/lld/dist-release_60/test/ELF/mips-26-n32-n64.s Wed Jun 27 19:15:02 2018 (r335728) @@ -5,8 +5,12 @@ # RUN: ld.lld %t-so.o -shared -o %t.so # RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux %s -o %t.o # RUN: ld.lld %t.o %t.so -o %t.exe -# RUN: llvm-objdump -d %t.exe | FileCheck %s +# RUN: llvm-objdump -d %t.exe | FileCheck %s --check-prefixes=CHECK,DEFAULT +# RUN: ld.lld %t-so.o -shared -o %t.so -z hazardplt +# RUN: ld.lld %t.o %t.so -o %t.exe -z hazardplt +# RUN: llvm-objdump -d %t.exe | FileCheck %s --check-prefixes=CHECK,HAZARDPLT + # REQUIRES: mips # CHECK: Disassembly of section .text: @@ -21,11 +25,13 @@ # CHECK-NEXT: 2001c: 03 0e c0 23 subu $24, $24, $14 # CHECK-NEXT: 20020: 03 e0 78 25 move $15, $ra # CHECK-NEXT: 20024: 00 18 c0 c2 srl $24, $24, 3 -# CHECK-NEXT: 20028: 03 20 f8 09 jalr $25 +# DEFAULT: 20028: 03 20 f8 09 jalr $25 +# HAZARDPLT: 20028: 03 20 fc 09 jalr.hb $25 # CHECK-NEXT: 2002c: 27 18 ff fe addiu $24, $24, -2 # CHECK-NEXT: 20030: 3c 0f 00 03 lui $15, 3 # CHECK-NEXT: 20034: 8d f9 00 18 lw $25, 24($15) -# CHECK-NEXT: 20038: 03 20 00 08 jr $25 +# DEFAULT: 20038: 03 20 00 08 jr $25 +# HAZARDPLT: 20038: 03 20 04 08 jr.hb $25 # CHECK-NEXT: 2003c: 25 f8 00 18 addiu $24, $15, 24 .text Modified: vendor/lld/dist-release_60/test/ELF/mips-plt-r6.s ============================================================================== --- vendor/lld/dist-release_60/test/ELF/mips-plt-r6.s Wed Jun 27 19:14:58 2018 (r335727) +++ vendor/lld/dist-release_60/test/ELF/mips-plt-r6.s Wed Jun 27 19:15:02 2018 (r335728) @@ -6,7 +6,10 @@ # RUN: -mcpu=mips32r6 %S/Inputs/mips-dynamic.s -o %t2.o # RUN: ld.lld %t2.o -shared -o %t.so # RUN: ld.lld %t1.o %t.so -o %t.exe -# RUN: llvm-objdump -d %t.exe | FileCheck %s +# RUN: llvm-objdump -d %t.exe | FileCheck %s --check-prefixes=DEFAULT,CHECK +# RUN: ld.lld %t2.o -shared -o %t.so -z hazardplt +# RUN: ld.lld %t1.o %t.so -o %t.exe -z hazardplt +# RUN: llvm-objdump -d %t.exe | FileCheck %s --check-prefixes=HAZARDPLT,CHECK # REQUIRES: mips @@ -24,12 +27,14 @@ # CHECK-NEXT: 2001c: 03 1c c0 23 subu $24, $24, $gp # CHECK-NEXT: 20020: 03 e0 78 25 move $15, $ra # CHECK-NEXT: 20024: 00 18 c0 82 srl $24, $24, 2 -# CHECK-NEXT: 20028: 03 20 f8 09 jalr $25 +# DEFAULT: 20028: 03 20 f8 09 jalr $25 +# HAZARDPLT: 20028: 03 20 fc 09 jalr.hb $25 # CHECK-NEXT: 2002c: 27 18 ff fe addiu $24, $24, -2 # CHECK-NEXT: 20030: 3c 0f 00 03 aui $15, $zero, 3 # CHECK-NEXT: 20034: 8d f9 00 0c lw $25, 12($15) -# CHECK-NEXT: 20038: 03 20 00 09 jr $25 +# DEFAULT: 20038: 03 20 00 09 jr $25 +# HAZARDPLT: 20038: 03 20 04 09 jr.hb $25 # CHECK-NEXT: 2003c: 25 f8 00 0c addiu $24, $15, 12 .text Modified: vendor/lld/dist-release_60/test/MinGW/driver.test ============================================================================== --- vendor/lld/dist-release_60/test/MinGW/driver.test Wed Jun 27 19:14:58 2018 (r335727) +++ vendor/lld/dist-release_60/test/MinGW/driver.test Wed Jun 27 19:15:02 2018 (r335728) @@ -124,3 +124,7 @@ ICF-NONE: -opt:noicf RUN: ld.lld -### -m i386pep foo.o --icf=all | FileCheck -check-prefix ICF %s RUN: ld.lld -### -m i386pep foo.o -icf=all | FileCheck -check-prefix ICF %s ICF: -opt:icf + +RUN: ld.lld -### foo.o -m i386pe -shared --kill-at | FileCheck -check-prefix=KILL-AT %s +RUN: ld.lld -### foo.o -m i386pe -shared -kill-at | FileCheck -check-prefix=KILL-AT %s +KILL-AT: -kill-at From owner-svn-src-vendor@freebsd.org Wed Jun 27 19:15:03 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 8F91E10030B5; Wed, 27 Jun 2018 19:15:03 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id D28B28DF0F; Wed, 27 Jun 2018 19:14:59 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 7BCAB27300; Wed, 27 Jun 2018 19:14:59 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5RJExaZ043192; Wed, 27 Jun 2018 19:14:59 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5RJExge043191; Wed, 27 Jun 2018 19:14:59 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201806271914.w5RJExge043191@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 27 Jun 2018 19:14:59 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335727 - vendor/libc++/libc++-release_601-r335540 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/libc++/libc++-release_601-r335540 X-SVN-Commit-Revision: 335727 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jun 2018 19:15:03 -0000 Author: dim Date: Wed Jun 27 19:14:58 2018 New Revision: 335727 URL: https://svnweb.freebsd.org/changeset/base/335727 Log: Tag libc++ 6.0.1 release r335540. Added: vendor/libc++/libc++-release_601-r335540/ - copied from r335726, vendor/libc++/dist-release_60/ From owner-svn-src-vendor@freebsd.org Wed Jun 27 19:15:12 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 2A2BE1003114; Wed, 27 Jun 2018 19:15:12 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id BDA608E064; Wed, 27 Jun 2018 19:15:09 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id E81F427302; Wed, 27 Jun 2018 19:15:08 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5RJF8rr043315; Wed, 27 Jun 2018 19:15:08 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5RJF80q043314; Wed, 27 Jun 2018 19:15:08 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201806271915.w5RJF80q043314@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 27 Jun 2018 19:15:08 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335729 - vendor/lld/lld-release_601-r335540 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/lld/lld-release_601-r335540 X-SVN-Commit-Revision: 335729 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jun 2018 19:15:12 -0000 Author: dim Date: Wed Jun 27 19:15:08 2018 New Revision: 335729 URL: https://svnweb.freebsd.org/changeset/base/335729 Log: Tag lld 6.0.1 release r335540. Added: vendor/lld/lld-release_601-r335540/ - copied from r335728, vendor/lld/dist-release_60/ From owner-svn-src-vendor@freebsd.org Wed Jun 27 19:15:16 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id B5EA41003159; Wed, 27 Jun 2018 19:15:16 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id EBBDB8E14C; Wed, 27 Jun 2018 19:15:14 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4C2E927303; Wed, 27 Jun 2018 19:15:14 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5RJFEC5043363; Wed, 27 Jun 2018 19:15:14 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5RJFE0m043362; Wed, 27 Jun 2018 19:15:14 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201806271915.w5RJFE0m043362@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 27 Jun 2018 19:15:14 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335730 - vendor/lldb/dist-release_60/cmake/modules X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/lldb/dist-release_60/cmake/modules X-SVN-Commit-Revision: 335730 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jun 2018 19:15:16 -0000 Author: dim Date: Wed Jun 27 19:15:13 2018 New Revision: 335730 URL: https://svnweb.freebsd.org/changeset/base/335730 Log: Vendor import of lldb 6.0.1 release r335540: https://llvm.org/svn/llvm-project/lldb/tags/RELEASE_601/final@335540 Modified: vendor/lldb/dist-release_60/cmake/modules/LLDBConfig.cmake Modified: vendor/lldb/dist-release_60/cmake/modules/LLDBConfig.cmake ============================================================================== --- vendor/lldb/dist-release_60/cmake/modules/LLDBConfig.cmake Wed Jun 27 19:15:08 2018 (r335729) +++ vendor/lldb/dist-release_60/cmake/modules/LLDBConfig.cmake Wed Jun 27 19:15:13 2018 (r335730) @@ -277,27 +277,31 @@ include_directories(BEFORE if (NOT LLVM_INSTALL_TOOLCHAIN_ONLY) install(DIRECTORY include/ - COMPONENT lldb_headers + COMPONENT lldb-headers DESTINATION include FILES_MATCHING PATTERN "*.h" PATTERN ".svn" EXCLUDE PATTERN ".cmake" EXCLUDE PATTERN "Config.h" EXCLUDE - PATTERN "lldb-*.h" EXCLUDE - PATTERN "API/*.h" EXCLUDE ) install(DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/include/ - COMPONENT lldb_headers + COMPONENT lldb-headers DESTINATION include FILES_MATCHING PATTERN "*.h" PATTERN ".svn" EXCLUDE PATTERN ".cmake" EXCLUDE - PATTERN "lldb-*.h" EXCLUDE - PATTERN "API/*.h" EXCLUDE ) + + add_custom_target(lldb-headers) + set_target_properties(lldb-headers PROPERTIES FOLDER "Misc") + + if (NOT CMAKE_CONFIGURATION_TYPES) + add_llvm_install_targets(install-lldb-headers + COMPONENT lldb-headers) + endif() endif() if (NOT LIBXML2_FOUND AND NOT (CMAKE_SYSTEM_NAME MATCHES "Windows")) From owner-svn-src-vendor@freebsd.org Wed Jun 27 19:15:19 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id B9A971003175; Wed, 27 Jun 2018 19:15:19 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 883918E1A7; Wed, 27 Jun 2018 19:15:18 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 06F9B27304; Wed, 27 Jun 2018 19:15:18 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5RJFHEL043411; Wed, 27 Jun 2018 19:15:17 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5RJFHXa043410; Wed, 27 Jun 2018 19:15:17 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201806271915.w5RJFHXa043410@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 27 Jun 2018 19:15:17 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335731 - vendor/lldb/lldb-release_601-r335540 X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: vendor/lldb/lldb-release_601-r335540 X-SVN-Commit-Revision: 335731 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jun 2018 19:15:19 -0000 Author: dim Date: Wed Jun 27 19:15:17 2018 New Revision: 335731 URL: https://svnweb.freebsd.org/changeset/base/335731 Log: Tag lldb 6.0.1 release r335540. Added: vendor/lldb/lldb-release_601-r335540/ - copied from r335730, vendor/lldb/dist-release_60/ From owner-svn-src-vendor@freebsd.org Fri Jun 29 20:17:02 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 9BBFDF7826F; Fri, 29 Jun 2018 20:17:02 +0000 (UTC) (envelope-from jkim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 3A98D79C7D; Fri, 29 Jun 2018 20:17:02 +0000 (UTC) (envelope-from jkim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 176F72597F; Fri, 29 Jun 2018 20:17:02 +0000 (UTC) (envelope-from jkim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5TKH1kS093974; Fri, 29 Jun 2018 20:17:01 GMT (envelope-from jkim@FreeBSD.org) Received: (from jkim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5TKGvJL093947; Fri, 29 Jun 2018 20:16:57 GMT (envelope-from jkim@FreeBSD.org) Message-Id: <201806292016.w5TKGvJL093947@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jkim set sender to jkim@FreeBSD.org using -f From: Jung-uk Kim Date: Fri, 29 Jun 2018 20:16:57 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335802 - in vendor-sys/acpica/dist: . source/common source/compiler source/components/hardware source/components/namespace source/include source/tools/acpisrc X-SVN-Group: vendor-sys X-SVN-Commit-Author: jkim X-SVN-Commit-Paths: in vendor-sys/acpica/dist: . source/common source/compiler source/components/hardware source/components/namespace source/include source/tools/acpisrc X-SVN-Commit-Revision: 335802 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jun 2018 20:17:03 -0000 Author: jkim Date: Fri Jun 29 20:16:57 2018 New Revision: 335802 URL: https://svnweb.freebsd.org/changeset/base/335802 Log: Import ACPICA 20180629. Modified: vendor-sys/acpica/dist/changes.txt vendor-sys/acpica/dist/source/common/dmextern.c vendor-sys/acpica/dist/source/compiler/aslglobal.h vendor-sys/acpica/dist/source/compiler/aslhelpers.y vendor-sys/acpica/dist/source/compiler/aslload.c vendor-sys/acpica/dist/source/compiler/aslmain.c vendor-sys/acpica/dist/source/compiler/aslmessages.c vendor-sys/acpica/dist/source/compiler/aslmessages.h vendor-sys/acpica/dist/source/compiler/asloptions.c vendor-sys/acpica/dist/source/compiler/aslparser.y vendor-sys/acpica/dist/source/compiler/aslprimaries.y vendor-sys/acpica/dist/source/compiler/asltransform.c vendor-sys/acpica/dist/source/compiler/asltypes.y vendor-sys/acpica/dist/source/components/hardware/hwxfsleep.c vendor-sys/acpica/dist/source/components/namespace/nsaccess.c vendor-sys/acpica/dist/source/components/namespace/nseval.c vendor-sys/acpica/dist/source/components/namespace/nssearch.c vendor-sys/acpica/dist/source/include/aclocal.h vendor-sys/acpica/dist/source/include/acpixf.h vendor-sys/acpica/dist/source/tools/acpisrc/asconvrt.c Modified: vendor-sys/acpica/dist/changes.txt ============================================================================== --- vendor-sys/acpica/dist/changes.txt Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/changes.txt Fri Jun 29 20:16:57 2018 (r335802) @@ -1,4 +1,63 @@ ---------------------------------------- +29 June 2018. Summary of changes for version 20180629: + + +1) iASL Compiler/Disassembler and Tools: + +iASL: Fixed a regression related to the use of the ASL External +statement. Error checking for the use of the External() statement has +been relaxed. Previously, a restriction on the use of External meant that +the referenced named object was required to be defined in a different +table (an SSDT). Thus it would be an error to declare an object as an +external and then define the same named object in the same table. For +example: + DefinitionBlock (...) + { + External (DEV1) + Device (DEV1){...} // This was an error + } +However, this behavior has caused regressions in some existing ASL code, +because there is code that depends on named objects and externals (with +the same name) being declared in the same table. This change will allow +the ASL code above to compile without errors or warnings. + +iASL: Implemented ASL language extensions for four operators to make some +of their arguments optional instead of required: + 1) Field (RegionName, AccessType, LockRule, UpdateRule) + 2) BankField (RegionName, BankName, BankValue, + AccessType, LockRule, UpdateRule) + 3) IndexField (IndexName, DataName, + AccessType, LockRule, UpdateRule) +For the Field operators above, the AccessType, LockRule, and UpdateRule +are now optional arguments. The default values are: + AccessType: AnyAcc + LockRule: NoLock + UpdateRule: Preserve + 4) Mutex (MutexName, SyncLevel) +For this operator, the SyncLevel argument is now optional. This argument +is rarely used in any meaningful way by ASL code, and thus it makes sense +to make it optional. The default value is: + SyncLevel: 0 + +iASL: Attempted use of the ASL Unload() operator now results in the +following warning: + "Unload is not supported by all operating systems" +This is in fact very true, and the Unload operator may be completely +deprecated in the near future. + +AcpiExec: Fixed a regression for the -fi option (Namespace initialization +file. Recent changes in the ACPICA module-level code support altered the +table load/initialization sequence . This means that the table load has +become a large method execution of the table itself. If Operation Region +Fields are used within any module-level code and the -fi option was +specified, the initialization values were populated only after the table +had completely finished loading (and thus the module-level code had +already been executed). This change moves the initialization of objects +listed in the initialization file to before the table is executed as a +method. Field unit values are now initialized before the table execution +is performed. + +---------------------------------------- 31 May 2018. Summary of changes for version 20180531: Modified: vendor-sys/acpica/dist/source/common/dmextern.c ============================================================================== --- vendor-sys/acpica/dist/source/common/dmextern.c Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/common/dmextern.c Fri Jun 29 20:16:57 2018 (r335802) @@ -538,7 +538,7 @@ AcpiDmGetExternalsFromFile ( /* Each line defines a method */ - while (fgets (StringBuffer, ASL_MSG_BUFFER_SIZE, ExternalRefFile)) + while (fgets (StringBuffer, ASL_STRING_BUFFER_SIZE, ExternalRefFile)) { Token = strtok (StringBuffer, METHOD_SEPARATORS); /* "External" */ if (!Token) Modified: vendor-sys/acpica/dist/source/compiler/aslglobal.h ============================================================================== --- vendor-sys/acpica/dist/source/compiler/aslglobal.h Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/compiler/aslglobal.h Fri Jun 29 20:16:57 2018 (r335802) @@ -251,7 +251,8 @@ extern int AslCompilerdebug; #define ASL_DEFAULT_LINE_BUFFER_SIZE (1024 * 32) /* 32K */ -#define ASL_MSG_BUFFER_SIZE (1024 * 32) /* 32k */ +#define ASL_MSG_BUFFER_SIZE (1024 * 128) /* 128k */ +#define ASL_STRING_BUFFER_SIZE (1024 * 32) /* 32k */ #define ASL_MAX_DISABLED_MESSAGES 32 #define ASL_MAX_EXPECTED_MESSAGES 32 #define HEX_TABLE_LINE_SIZE 8 @@ -438,8 +439,8 @@ ASL_EXTERN UINT8 AslGbl_NamespaceEv ASL_EXTERN UINT8 Gbl_AmlBuffer[HEX_LISTING_LINE_SIZE]; ASL_EXTERN char MsgBuffer[ASL_MSG_BUFFER_SIZE]; -ASL_EXTERN char StringBuffer[ASL_MSG_BUFFER_SIZE]; -ASL_EXTERN char StringBuffer2[ASL_MSG_BUFFER_SIZE]; +ASL_EXTERN char StringBuffer[ASL_STRING_BUFFER_SIZE]; +ASL_EXTERN char StringBuffer2[ASL_STRING_BUFFER_SIZE]; ASL_EXTERN UINT32 Gbl_DisabledMessages[ASL_MAX_DISABLED_MESSAGES]; ASL_EXTERN ASL_EXPECTED_MESSAGE Gbl_ExpectedMessages[ASL_MAX_EXPECTED_MESSAGES]; Modified: vendor-sys/acpica/dist/source/compiler/aslhelpers.y ============================================================================== --- vendor-sys/acpica/dist/source/compiler/aslhelpers.y Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/compiler/aslhelpers.y Fri Jun 29 20:16:57 2018 (r335802) @@ -183,6 +183,14 @@ OptionalAccessSize | ',' ByteConstExpr {$$ = $2;} ; +OptionalAccessTypeKeyword /* Default: AnyAcc */ + : {$$ = TrCreateLeafOp ( + PARSEOP_ACCESSTYPE_ANY);} + | ',' {$$ = TrCreateLeafOp ( + PARSEOP_ACCESSTYPE_ANY);} + | ',' AccessTypeKeyword {$$ = $2;} + ; + OptionalAddressingMode : ',' {$$ = NULL;} | ',' AddressingModeKeyword {$$ = $2;} @@ -252,6 +260,14 @@ OptionalListString | ',' TermArg {$$ = $2;} ; +OptionalLockRuleKeyword /* Default: NoLock */ + : {$$ = TrCreateLeafOp ( + PARSEOP_LOCKRULE_NOLOCK);} + | ',' {$$ = TrCreateLeafOp ( + PARSEOP_LOCKRULE_NOLOCK);} + | ',' LockRuleKeyword {$$ = $2;} + ; + OptionalMaxType : ',' {$$ = NULL;} | ',' MaxKeyword {$$ = $2;} @@ -366,6 +382,14 @@ OptionalStringData | ',' StringData {$$ = $2;} ; +OptionalSyncLevel /* Default: 0 */ + : {$$ = TrCreateValuedLeafOp ( + PARSEOP_BYTECONST, 0);} + | ',' {$$ = TrCreateValuedLeafOp ( + PARSEOP_BYTECONST, 0);} + | ',' ByteConstExpr {$$ = $2;} + ; + OptionalTranslationType_Last : {$$ = NULL;} | ',' {$$ = NULL;} @@ -382,6 +406,14 @@ OptionalType_Last : {$$ = NULL;} | ',' {$$ = NULL;} | ',' TypeKeyword {$$ = $2;} + ; + +OptionalUpdateRuleKeyword /* Default: Preserve */ + : {$$ = TrCreateLeafOp ( + PARSEOP_UPDATERULE_PRESERVE);} + | ',' {$$ = TrCreateLeafOp ( + PARSEOP_UPDATERULE_PRESERVE);} + | ',' UpdateRuleKeyword {$$ = $2;} ; OptionalWireMode Modified: vendor-sys/acpica/dist/source/compiler/aslload.c ============================================================================== --- vendor-sys/acpica/dist/source/compiler/aslload.c Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/compiler/aslload.c Fri Jun 29 20:16:57 2018 (r335802) @@ -321,8 +321,7 @@ LdLoadFieldElements ( return (Status); } else if (Status == AE_ALREADY_EXISTS && - (Node->Flags & ANOBJ_IS_EXTERNAL) && - Node->OwnerId != WalkState->OwnerId) + (Node->Flags & ANOBJ_IS_EXTERNAL)) { Node->Type = (UINT8) ACPI_TYPE_LOCAL_REGION_FIELD; } @@ -474,7 +473,6 @@ LdNamespace1Begin ( ACPI_PARSE_OBJECT *Arg; UINT32 i; BOOLEAN ForceNewScope = FALSE; - ACPI_OWNER_ID OwnerId = 0; const ACPI_OPCODE_INFO *OpInfo; ACPI_PARSE_OBJECT *ParentOp; @@ -485,23 +483,6 @@ LdNamespace1Begin ( ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "Op %p [%s]\n", Op, Op->Asl.ParseOpName)); - if (Op->Asl.ParseOpcode == PARSEOP_DEFINITION_BLOCK) - { - /* - * Allocate an OwnerId for this block. This helps identify the owners - * of each namespace node. This is used in determining whether if - * certain external declarations cause redefinition errors. - */ - Status = AcpiUtAllocateOwnerId (&OwnerId); - WalkState->OwnerId = OwnerId; - if (ACPI_FAILURE (Status)) - { - AslCoreSubsystemError (Op, Status, - "Failure to allocate owner ID to this definition block.", FALSE); - return_ACPI_STATUS (Status); - } - } - /* * We are only interested in opcodes that have an associated name * (or multiple names) @@ -877,9 +858,7 @@ LdNamespace1Begin ( { /* * Allow one create on an object or segment that was - * previously declared External only if WalkState->OwnerId and - * Node->OwnerId are different (meaning that the current WalkState - * and the Node are in different tables). + * previously declared External */ Node->Flags &= ~ANOBJ_IS_EXTERNAL; Node->Type = (UINT8) ObjectType; @@ -896,18 +875,6 @@ LdNamespace1Begin ( } Status = AE_OK; - - if (Node->OwnerId == WalkState->OwnerId && - !(Node->Flags & IMPLICIT_EXTERNAL)) - { - AslDualParseOpError (ASL_WARNING, ASL_MSG_EXTERN_COLLISION, Op, - Op->Asl.ExternalName, ASL_MSG_EXTERN_FOUND_HERE, Node->Op, - Node->Op->Asl.ExternalName); - } - if (Node->Flags & IMPLICIT_EXTERNAL) - { - Node->Flags &= ~IMPLICIT_EXTERNAL; - } } else if (!(Node->Flags & ANOBJ_IS_EXTERNAL) && (Op->Asl.ParseOpcode == PARSEOP_EXTERNAL)) @@ -915,53 +882,15 @@ LdNamespace1Begin ( /* * Allow externals in same scope as the definition of the * actual object. Similar to C. Allows multiple definition - * blocks that refer to each other in the same file. However, - * do not allow name declaration and an external declaration - * within the same table. This is considered a re-declaration. + * blocks that refer to each other in the same file. */ Status = AE_OK; - - if (Node->OwnerId == WalkState->OwnerId) - { - AslDualParseOpError (ASL_WARNING, ASL_MSG_EXTERN_COLLISION, Op, - Op->Asl.ExternalName, ASL_MSG_EXTERN_FOUND_HERE, Node->Op, - Node->Op->Asl.ExternalName); - } } else if ((Node->Flags & ANOBJ_IS_EXTERNAL) && (Op->Asl.ParseOpcode == PARSEOP_EXTERNAL) && (ObjectType == ACPI_TYPE_ANY)) { - /* - * Allow update of externals of unknown type. - * In the case that multiple definition blocks are being - * parsed, updating the OwnerId allows enables subsequent calls - * of this method to understand which table the most recent - * external declaration was seen. Without this OwnerId update, - * code like the following is allowed to compile: - * - * DefinitionBlock("externtest.aml", "DSDT", 0x02, "Intel", "Many", 0x00000001) - * { - * External(ERRS,methodobj) - * Method (MAIN) - * { - * Name(NUM2, 0) - * ERRS(1,2,3) - * } - * } - * - * DefinitionBlock("externtest.aml", "SSDT", 0x02, "Intel", "Many", 0x00000001) - * { - * if (0) - * { - * External(ERRS,methodobj) - * } - * Method (ERRS,3) - * {} - * - * } - */ - Node->OwnerId = WalkState->OwnerId; + /* Allow update of externals of unknown type. */ if (AcpiNsOpensScope (ActualObjectType)) { Modified: vendor-sys/acpica/dist/source/compiler/aslmain.c ============================================================================== --- vendor-sys/acpica/dist/source/compiler/aslmain.c Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/compiler/aslmain.c Fri Jun 29 20:16:57 2018 (r335802) @@ -208,7 +208,6 @@ main ( signal (SIGINT, AslSignalHandler); - signal (SIGSEGV, AslSignalHandler); /* * Big-endian machines are not currently supported. ACPI tables must @@ -306,8 +305,7 @@ CleanupAndExit: * * DESCRIPTION: Signal interrupt handler. Delete any intermediate files and * any output files that may be left in an indeterminate state. - * Currently handles SIGINT (control-c) and SIGSEGV (segmentation - * fault). + * Currently handles SIGINT (control-c). * *****************************************************************************/ @@ -329,17 +327,10 @@ AslSignalHandler ( printf ("\n" ASL_PREFIX "\n"); break; - case SIGSEGV: - - /* Even on a seg fault, we will try to delete any partial files */ - - printf (ASL_PREFIX "Segmentation Fault\n"); - break; - default: - printf (ASL_PREFIX "Unknown interrupt signal (%u), ignoring\n", Sig); - return; + printf (ASL_PREFIX "Unknown interrupt signal (%u)\n", Sig); + break; } /* Modified: vendor-sys/acpica/dist/source/compiler/aslmessages.c ============================================================================== --- vendor-sys/acpica/dist/source/compiler/aslmessages.c Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/compiler/aslmessages.c Fri Jun 29 20:16:57 2018 (r335802) @@ -356,7 +356,8 @@ const char *AslCompilerMsgs [] = /* ASL_MSG_EXTERN_COLLISION */ "A name cannot be defined and declared external in the same table", /* ASL_MSG_FOUND_HERE_EXTERN */ "Remove one of the declarations indicated above or below:", /* ASL_MSG_OEM_TABLE_ID */ "Invalid OEM Table ID", -/* ASL_MSG_OEM_ID */ "Invalid OEM ID" +/* ASL_MSG_OEM_ID */ "Invalid OEM ID", +/* ASL_MSG_UNLOAD */ "Unload is not supported by all operating systems" }; /* Table compiler */ Modified: vendor-sys/acpica/dist/source/compiler/aslmessages.h ============================================================================== --- vendor-sys/acpica/dist/source/compiler/aslmessages.h Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/compiler/aslmessages.h Fri Jun 29 20:16:57 2018 (r335802) @@ -359,6 +359,7 @@ typedef enum ASL_MSG_EXTERN_FOUND_HERE, ASL_MSG_OEM_TABLE_ID, ASL_MSG_OEM_ID, + ASL_MSG_UNLOAD, /* These messages are used by the Data Table compiler only */ Modified: vendor-sys/acpica/dist/source/compiler/asloptions.c ============================================================================== --- vendor-sys/acpica/dist/source/compiler/asloptions.c Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/compiler/asloptions.c Fri Jun 29 20:16:57 2018 (r335802) @@ -1080,7 +1080,7 @@ AslDoResponseFile ( * Process all lines in the response file. There must be one complete * option per line */ - while (fgets (StringBuffer, ASL_MSG_BUFFER_SIZE, ResponseFile)) + while (fgets (StringBuffer, ASL_STRING_BUFFER_SIZE, ResponseFile)) { /* Compress all tokens, allowing us to use a single argv entry */ Modified: vendor-sys/acpica/dist/source/compiler/aslparser.y ============================================================================== --- vendor-sys/acpica/dist/source/compiler/aslparser.y Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/compiler/aslparser.y Fri Jun 29 20:16:57 2018 (r335802) @@ -208,7 +208,7 @@ AslLocalAllocate ( * These shift/reduce conflicts are expected. There should be zero * reduce/reduce conflicts. */ -%expect 118 +%expect 124 /*! [Begin] no source code translation */ Modified: vendor-sys/acpica/dist/source/compiler/aslprimaries.y ============================================================================== --- vendor-sys/acpica/dist/source/compiler/aslprimaries.y Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/compiler/aslprimaries.y Fri Jun 29 20:16:57 2018 (r335802) @@ -235,12 +235,12 @@ BankFieldTerm NameString NameStringItem TermArgItem - ',' AccessTypeKeyword - ',' LockRuleKeyword - ',' UpdateRuleKeyword + OptionalAccessTypeKeyword + OptionalLockRuleKeyword + OptionalUpdateRuleKeyword PARSEOP_CLOSE_PAREN '{' FieldUnitList '}' {$$ = TrLinkOpChildren ($3,7, - $4,$5,$6,$8,$10,$12,$15);} + $4,$5,$6,$7,$8,$9,$12);} | PARSEOP_BANKFIELD PARSEOP_OPEN_PAREN error PARSEOP_CLOSE_PAREN @@ -579,11 +579,11 @@ FieldTerm : PARSEOP_FIELD PARSEOP_OPEN_PAREN {$$ = TrCreateLeafOp (PARSEOP_FIELD);} NameString - ',' AccessTypeKeyword - ',' LockRuleKeyword - ',' UpdateRuleKeyword + OptionalAccessTypeKeyword + OptionalLockRuleKeyword + OptionalUpdateRuleKeyword PARSEOP_CLOSE_PAREN '{' - FieldUnitList '}' {$$ = TrLinkOpChildren ($3,5,$4,$6,$8,$10,$13);} + FieldUnitList '}' {$$ = TrLinkOpChildren ($3,5,$4,$5,$6,$7,$10);} | PARSEOP_FIELD PARSEOP_OPEN_PAREN error PARSEOP_CLOSE_PAREN @@ -711,11 +711,11 @@ IndexFieldTerm PARSEOP_OPEN_PAREN {$$ = TrCreateLeafOp (PARSEOP_INDEXFIELD);} NameString NameStringItem - ',' AccessTypeKeyword - ',' LockRuleKeyword - ',' UpdateRuleKeyword + OptionalAccessTypeKeyword + OptionalLockRuleKeyword + OptionalUpdateRuleKeyword PARSEOP_CLOSE_PAREN '{' - FieldUnitList '}' {$$ = TrLinkOpChildren ($3,6,$4,$5,$7,$9,$11,$14);} + FieldUnitList '}' {$$ = TrLinkOpChildren ($3,6,$4,$5,$6,$7,$8,$11);} | PARSEOP_INDEXFIELD PARSEOP_OPEN_PAREN error PARSEOP_CLOSE_PAREN @@ -946,9 +946,9 @@ MutexTerm : PARSEOP_MUTEX PARSEOP_OPEN_PAREN {$$ = TrCreateLeafOp (PARSEOP_MUTEX);} NameString - ',' ByteConstExpr + OptionalSyncLevel PARSEOP_CLOSE_PAREN {$$ = TrLinkOpChildren ($3,2, - TrSetOpFlags ($4, OP_IS_NAME_DECLARATION),$6);} + TrSetOpFlags ($4, OP_IS_NAME_DECLARATION),$5);} | PARSEOP_MUTEX PARSEOP_OPEN_PAREN error PARSEOP_CLOSE_PAREN {$$ = AslDoError(); yyclearin;} Modified: vendor-sys/acpica/dist/source/compiler/asltransform.c ============================================================================== --- vendor-sys/acpica/dist/source/compiler/asltransform.c Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/compiler/asltransform.c Fri Jun 29 20:16:57 2018 (r335802) @@ -496,6 +496,11 @@ TrTransformSubtree ( Op->Asl.Value.String = "\\"; break; + case PARSEOP_UNLOAD: + + AslError (ASL_WARNING, ASL_MSG_UNLOAD, Op, NULL); + break; + default: /* Nothing to do here for other opcodes */ Modified: vendor-sys/acpica/dist/source/compiler/asltypes.y ============================================================================== --- vendor-sys/acpica/dist/source/compiler/asltypes.y Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/compiler/asltypes.y Fri Jun 29 20:16:57 2018 (r335802) @@ -461,6 +461,7 @@ NoEcho(' %type TermArgItem %type OptionalAccessSize +%type OptionalAccessTypeKeyword %type OptionalAddressingMode %type OptionalAddressRange %type OptionalBitsPerByte @@ -475,6 +476,7 @@ NoEcho(' %type OptionalFlowControl %type OptionalIoRestriction %type OptionalListString +%type OptionalLockRuleKeyword %type OptionalMaxType %type OptionalMemType %type OptionalMinType @@ -500,10 +502,12 @@ NoEcho(' %type OptionalSlaveMode %type OptionalStopBits %type OptionalStringData +%type OptionalSyncLevel %type OptionalTermArg %type OptionalTranslationType_Last %type OptionalType %type OptionalType_Last +%type OptionalUpdateRuleKeyword %type OptionalWireMode %type OptionalWordConst %type OptionalWordConstExpr Modified: vendor-sys/acpica/dist/source/components/hardware/hwxfsleep.c ============================================================================== --- vendor-sys/acpica/dist/source/components/hardware/hwxfsleep.c Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/components/hardware/hwxfsleep.c Fri Jun 29 20:16:57 2018 (r335802) @@ -184,17 +184,17 @@ AcpiHwSleepDispatch ( static ACPI_SLEEP_FUNCTIONS AcpiSleepDispatch[] = { - {ACPI_STRUCT_INIT (legacy_function, + {ACPI_STRUCT_INIT (LegacyFunction, ACPI_HW_OPTIONAL_FUNCTION (AcpiHwLegacySleep)), - ACPI_STRUCT_INIT (extended_function, + ACPI_STRUCT_INIT (ExtendedFunction, AcpiHwExtendedSleep) }, - {ACPI_STRUCT_INIT (legacy_function, + {ACPI_STRUCT_INIT (LegacyFunction, ACPI_HW_OPTIONAL_FUNCTION (AcpiHwLegacyWakePrep)), - ACPI_STRUCT_INIT (extended_function, + ACPI_STRUCT_INIT (ExtendedFunction, AcpiHwExtendedWakePrep) }, - {ACPI_STRUCT_INIT (legacy_function, + {ACPI_STRUCT_INIT (Legacy_function, ACPI_HW_OPTIONAL_FUNCTION (AcpiHwLegacyWake)), - ACPI_STRUCT_INIT (extended_function, + ACPI_STRUCT_INIT (ExtendedFunction, AcpiHwExtendedWake) } }; Modified: vendor-sys/acpica/dist/source/components/namespace/nsaccess.c ============================================================================== --- vendor-sys/acpica/dist/source/components/namespace/nsaccess.c Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/components/namespace/nsaccess.c Fri Jun 29 20:16:57 2018 (r335802) @@ -781,13 +781,6 @@ AcpiNsLookup ( else { -#ifdef ACPI_ASL_COMPILER - if (!AcpiGbl_DisasmFlag && (ThisNode->Flags & ANOBJ_IS_EXTERNAL)) - { - ThisNode->Flags &= ~IMPLICIT_EXTERNAL; - } -#endif - /* * Sanity typecheck of the target object: * Modified: vendor-sys/acpica/dist/source/components/namespace/nseval.c ============================================================================== --- vendor-sys/acpica/dist/source/components/namespace/nseval.c Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/components/namespace/nseval.c Fri Jun 29 20:16:57 2018 (r335802) @@ -429,11 +429,11 @@ AcpiNsEvaluate ( Status = AE_OK; } - else if (ACPI_FAILURE(Status)) + else if (ACPI_FAILURE(Status)) { /* If ReturnObject exists, delete it */ - if (Info->ReturnObject) + if (Info->ReturnObject) { AcpiUtRemoveReference (Info->ReturnObject); Info->ReturnObject = NULL; Modified: vendor-sys/acpica/dist/source/components/namespace/nssearch.c ============================================================================== --- vendor-sys/acpica/dist/source/components/namespace/nssearch.c Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/components/namespace/nssearch.c Fri Jun 29 20:16:57 2018 (r335802) @@ -545,7 +545,6 @@ AcpiNsSearchAndEnter ( (WalkState && WalkState->Opcode == AML_SCOPE_OP)) { NewNode->Flags |= ANOBJ_IS_EXTERNAL; - NewNode->Flags |= IMPLICIT_EXTERNAL; } #endif Modified: vendor-sys/acpica/dist/source/include/aclocal.h ============================================================================== --- vendor-sys/acpica/dist/source/include/aclocal.h Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/include/aclocal.h Fri Jun 29 20:16:57 2018 (r335802) @@ -328,7 +328,6 @@ typedef struct acpi_namespace_node #define ANOBJ_EVALUATED 0x20 /* Set on first evaluation of node */ #define ANOBJ_ALLOCATED_BUFFER 0x40 /* Method AML buffer is dynamic (InstallMethod) */ -#define IMPLICIT_EXTERNAL 0x02 /* iASL only: This object created implicitly via External */ #define ANOBJ_IS_EXTERNAL 0x08 /* iASL only: This object created via External() */ #define ANOBJ_METHOD_NO_RETVAL 0x10 /* iASL only: Method has no return value */ #define ANOBJ_METHOD_SOME_NO_RETVAL 0x20 /* iASL only: Method has at least one return value */ Modified: vendor-sys/acpica/dist/source/include/acpixf.h ============================================================================== --- vendor-sys/acpica/dist/source/include/acpixf.h Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/include/acpixf.h Fri Jun 29 20:16:57 2018 (r335802) @@ -154,7 +154,7 @@ /* Current ACPICA subsystem version in YYYYMMDD format */ -#define ACPI_CA_VERSION 0x20180531 +#define ACPI_CA_VERSION 0x20180629 #include "acconfig.h" #include "actypes.h" Modified: vendor-sys/acpica/dist/source/tools/acpisrc/asconvrt.c ============================================================================== --- vendor-sys/acpica/dist/source/tools/acpisrc/asconvrt.c Fri Jun 29 19:35:25 2018 (r335801) +++ vendor-sys/acpica/dist/source/tools/acpisrc/asconvrt.c Fri Jun 29 20:16:57 2018 (r335802) @@ -183,7 +183,6 @@ AsCountLines ( char *Filename); - #define MODULE_HEADER_BEGIN "/******************************************************************************\n *\n * Module Name:"; #define MODULE_HEADER_END " *****************************************************************************/\n\n" #define INTEL_COPYRIGHT " * Copyright (C) 2000 - 2018, Intel Corp.\n" From owner-svn-src-vendor@freebsd.org Fri Jun 29 20:17:48 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 4DF60F78302; Fri, 29 Jun 2018 20:17:48 +0000 (UTC) (envelope-from jkim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 02B8979DE9; Fri, 29 Jun 2018 20:17:48 +0000 (UTC) (envelope-from jkim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id BE77D2598D; Fri, 29 Jun 2018 20:17:47 +0000 (UTC) (envelope-from jkim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5TKHlek094052; Fri, 29 Jun 2018 20:17:47 GMT (envelope-from jkim@FreeBSD.org) Received: (from jkim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5TKHlHK094051; Fri, 29 Jun 2018 20:17:47 GMT (envelope-from jkim@FreeBSD.org) Message-Id: <201806292017.w5TKHlHK094051@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jkim set sender to jkim@FreeBSD.org using -f From: Jung-uk Kim Date: Fri, 29 Jun 2018 20:17:47 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335803 - vendor-sys/acpica/20180629 X-SVN-Group: vendor-sys X-SVN-Commit-Author: jkim X-SVN-Commit-Paths: vendor-sys/acpica/20180629 X-SVN-Commit-Revision: 335803 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jun 2018 20:17:48 -0000 Author: jkim Date: Fri Jun 29 20:17:47 2018 New Revision: 335803 URL: https://svnweb.freebsd.org/changeset/base/335803 Log: Tag ACPICA 20180629. Added: vendor-sys/acpica/20180629/ - copied from r335802, vendor-sys/acpica/dist/