From owner-freebsd-arch@FreeBSD.ORG Thu Oct 25 13:51:00 2012 Return-Path: Delivered-To: freebsd-arch@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id D58A7A2B; Thu, 25 Oct 2012 13:51:00 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from bigwig.baldwin.cx (bigknife-pt.tunnel.tserv9.chi1.ipv6.he.net [IPv6:2001:470:1f10:75::2]) by mx1.freebsd.org (Postfix) with ESMTP id A93488FC1B; Thu, 25 Oct 2012 13:51:00 +0000 (UTC) Received: from jhbbsd.localnet (unknown [209.249.190.124]) by bigwig.baldwin.cx (Postfix) with ESMTPSA id 2011BB94B; Thu, 25 Oct 2012 09:51:00 -0400 (EDT) From: John Baldwin To: freebsd-arch@freebsd.org Subject: Re: CACHE_LINE_SIZE on x86 Date: Thu, 25 Oct 2012 09:18:00 -0400 User-Agent: KMail/1.13.5 (FreeBSD/8.2-CBSD-20110714-p20; KDE/4.5.5; amd64; ; ) References: In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201210250918.00602.jhb@freebsd.org> X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.7 (bigwig.baldwin.cx); Thu, 25 Oct 2012 09:51:00 -0400 (EDT) Cc: Jim Harris X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 25 Oct 2012 13:51:00 -0000 On Wednesday, October 24, 2012 3:13:38 pm Jim Harris wrote: > While investigating padding of the ULE scheduler locks (r242014), I > recently discovered that CACHE_LINE_SIZE on x86 is defined as 128 (not > 64). From what I can tell from svn logs, this was to account for 128 > byte cache "sectors" that existed on the NetBurst micro architecture > CPUs. > > I'm curious if there's been consideration in changing this back to 64? > With maybe a kernel config option to modify it? On 2S systems (but > not on 1S systems), I see a benefit using CACHE_LINE_SIZE=128 for the > scheduler locks. I suspect this is related to data prefetching but am > still running experiments to verify. All the i7 and later systems I've seen (maybe even Penryn?) have a BIOS option (typically enabled by default) to enable adjacent cache line prefetching (my understanding is that this only affects the LLC, and it seems to always fetch an aligned 128 bytes, so if your miss is in the "second" line it fetches N-1 and N, not always fetching N and N+1). That is why I thought we still use 128 bytes on x86. -- John Baldwin