From owner-svn-src-head@freebsd.org Fri Jul 3 17:54:42 2015 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id B0F8F9942BB; Fri, 3 Jul 2015 17:54:42 +0000 (UTC) (envelope-from loos@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 87B9B1AC5; Fri, 3 Jul 2015 17:54:42 +0000 (UTC) (envelope-from loos@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.70]) by repo.freebsd.org (8.14.9/8.14.9) with ESMTP id t63HsgBi049983; Fri, 3 Jul 2015 17:54:42 GMT (envelope-from loos@FreeBSD.org) Received: (from loos@localhost) by repo.freebsd.org (8.14.9/8.14.9/Submit) id t63HsfQZ049978; Fri, 3 Jul 2015 17:54:41 GMT (envelope-from loos@FreeBSD.org) Message-Id: <201507031754.t63HsfQZ049978@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: loos set sender to loos@FreeBSD.org using -f From: Luiz Otavio O Souza Date: Fri, 3 Jul 2015 17:54:41 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r285105 - head/sys/arm/allwinner X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 03 Jul 2015 17:54:42 -0000 Author: loos Date: Fri Jul 3 17:54:41 2015 New Revision: 285105 URL: https://svnweb.freebsd.org/changeset/base/285105 Log: Rename a10_emac_gpio_config() to a10_gpio_ethernet_activate() to make the change to GMAC easier on A20 SoCs. On A10 only the EMAC controller is available (fast ethernet), but on A20 there is also GMAC a high (or better) performant controller (gigabit ethernet). On A20 the both controllers uses the same pins to talk to the ethernet PHY (MII or RGMII) and they can be selected by the GPIO pin mux. There is work in progress to bring in GMAC support. Modified: head/sys/arm/allwinner/a10_gpio.c head/sys/arm/allwinner/a10_gpio.h head/sys/arm/allwinner/if_emac.c Modified: head/sys/arm/allwinner/a10_gpio.c ============================================================================== --- head/sys/arm/allwinner/a10_gpio.c Fri Jul 3 17:30:31 2015 (r285104) +++ head/sys/arm/allwinner/a10_gpio.c Fri Jul 3 17:54:41 2015 (r285105) @@ -524,8 +524,9 @@ static driver_t a10_gpio_driver = { DRIVER_MODULE(a10_gpio, simplebus, a10_gpio_driver, a10_gpio_devclass, 0, 0); int -a10_emac_gpio_config(uint32_t pin) +a10_gpio_ethernet_activate(uint32_t func) { + int i; struct a10_gpio_softc *sc = a10_gpio_sc; if (sc == NULL) @@ -533,7 +534,8 @@ a10_emac_gpio_config(uint32_t pin) /* Configure pin mux settings for MII. */ A10_GPIO_LOCK(sc); - a10_gpio_set_function(sc, pin, A10_GPIO_PULLDOWN); + for (i = 0; i <= 17; i++) + a10_gpio_set_function(sc, i, func); A10_GPIO_UNLOCK(sc); return (0); Modified: head/sys/arm/allwinner/a10_gpio.h ============================================================================== --- head/sys/arm/allwinner/a10_gpio.h Fri Jul 3 17:30:31 2015 (r285104) +++ head/sys/arm/allwinner/a10_gpio.h Fri Jul 3 17:54:41 2015 (r285105) @@ -29,6 +29,9 @@ #ifndef _A10_GPIO_H_ #define _A10_GPIO_H_ -int a10_emac_gpio_config(uint32_t pin); +#define A10_GPIO_FUNC_MII 2 +#define A10_GPIO_FUNC_RGMII 5 + +int a10_gpio_ethernet_activate(uint32_t); #endif Modified: head/sys/arm/allwinner/if_emac.c ============================================================================== --- head/sys/arm/allwinner/if_emac.c Fri Jul 3 17:30:31 2015 (r285104) +++ head/sys/arm/allwinner/if_emac.c Fri Jul 3 17:54:41 2015 (r285105) @@ -142,17 +142,12 @@ static int sysctl_hw_emac_proc_limit(SYS static void emac_sys_setup(void) { - int i; + /* Activate EMAC clock. */ a10_clk_emac_activate(); - - /* - * Configure pin mux settings for MII. - * Pins PA0 from PA17. - */ - for (i = 0; i <= 17; i++) - a10_emac_gpio_config(i); - /* Map sram */ + /* Set the pin mux to EMAC (mii). */ + a10_gpio_ethernet_activate(A10_GPIO_FUNC_MII); + /* Map sram. */ a10_map_to_emac(); }