Date: Mon, 21 May 2018 21:07:14 +0000 (UTC) From: Konstantin Belousov <kib@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r334004 - in head/sys/x86: include x86 Message-ID: <201805212107.w4LL7Ew1007440@repo.freebsd.org>
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Author: kib Date: Mon May 21 21:07:13 2018 New Revision: 334004 URL: https://svnweb.freebsd.org/changeset/base/334004 Log: Add definition for Intel Speculative Store Bypass Disable MSR bits Security: CVE-2018-3639 Sponsored by: The FreeBSD Foundation MFC after: 3 days Modified: head/sys/x86/include/specialreg.h head/sys/x86/x86/identcpu.c Modified: head/sys/x86/include/specialreg.h ============================================================================== --- head/sys/x86/include/specialreg.h Mon May 21 21:05:55 2018 (r334003) +++ head/sys/x86/include/specialreg.h Mon May 21 21:07:13 2018 (r334004) @@ -428,10 +428,12 @@ #define CPUID_STDEXT3_IBPB 0x04000000 #define CPUID_STDEXT3_STIBP 0x08000000 #define CPUID_STDEXT3_ARCH_CAP 0x20000000 +#define CPUID_STDEXT3_SSBD 0x80000000 /* MSR IA32_ARCH_CAP(ABILITIES) bits */ #define IA32_ARCH_CAP_RDCL_NO 0x00000001 #define IA32_ARCH_CAP_IBRS_ALL 0x00000002 +#define IA32_ARCH_CAP_SSBD_NO 0x00000004 /* * CPUID manufacturers identifiers @@ -704,6 +706,7 @@ /* MSR IA32_SPEC_CTRL */ #define IA32_SPEC_CTRL_IBRS 0x00000001 #define IA32_SPEC_CTRL_STIBP 0x00000002 +#define IA32_SPEC_CTRL_SSBD 0x00000004 /* MSR IA32_PRED_CMD */ #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL Modified: head/sys/x86/x86/identcpu.c ============================================================================== --- head/sys/x86/x86/identcpu.c Mon May 21 21:05:55 2018 (r334003) +++ head/sys/x86/x86/identcpu.c Mon May 21 21:07:13 2018 (r334004) @@ -990,6 +990,7 @@ printcpuinfo(void) "\033IBPB" "\034STIBP" "\036ARCH_CAP" + "\040SSBD" ); }
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