From owner-svn-src-head@FreeBSD.ORG Tue Mar 3 09:48:20 2015 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id D6E7E794; Tue, 3 Mar 2015 09:48:20 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id C260ADE4; Tue, 3 Mar 2015 09:48:20 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t239mKTO075838; Tue, 3 Mar 2015 09:48:20 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t239mKvK075837; Tue, 3 Mar 2015 09:48:20 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201503030948.t239mKvK075837@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Tue, 3 Mar 2015 09:48:20 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r279561 - head/sys/dev/uart X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Mar 2015 09:48:20 -0000 Author: andrew Date: Tue Mar 3 09:48:19 2015 New Revision: 279561 URL: https://svnweb.freebsd.org/changeset/base/279561 Log: Fix the pl011 driver to work when the uart will write in zero cycles. This is the case, depending on the options, in some of the ARM hardware simulators. In these cases we don't get an interrupt so will need to schedule the task to write more data to the uart. MFC after: 1 week Sponsored by: The FreeBSD Foundation Modified: head/sys/dev/uart/uart_dev_pl011.c Modified: head/sys/dev/uart/uart_dev_pl011.c ============================================================================== --- head/sys/dev/uart/uart_dev_pl011.c Tue Mar 3 07:51:36 2015 (r279560) +++ head/sys/dev/uart/uart_dev_pl011.c Tue Mar 3 09:48:19 2015 (r279561) @@ -452,15 +452,23 @@ uart_pl011_bus_transmit(struct uart_soft __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); uart_barrier(bas); } - sc->sc_txbusy = 1; - /* Enable TX interrupt */ - reg = __uart_getreg(bas, UART_IMSC); - reg |= (UART_TXEMPTY); - __uart_setreg(bas, UART_IMSC, reg); + /* If not empty wait until it is */ + if ((__uart_getreg(bas, UART_FR) & FR_TXFE) != FR_TXFE) { + sc->sc_txbusy = 1; + + /* Enable TX interrupt */ + reg = __uart_getreg(bas, UART_IMSC); + reg |= (UART_TXEMPTY); + __uart_setreg(bas, UART_IMSC, reg); + } uart_unlock(sc->sc_hwmtx); + /* No interrupt expected, schedule the next fifo write */ + if (!sc->sc_txbusy) + uart_sched_softih(sc, SER_INT_TXIDLE); + return (0); }