From owner-freebsd-arm@FreeBSD.ORG Sat Sep 6 01:15:37 2014 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 65145B1; Sat, 6 Sep 2014 01:15:37 +0000 (UTC) Received: from h2.funkthat.com (gate2.funkthat.com [208.87.223.18]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "funkthat.com", Issuer "funkthat.com" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 392011A93; Sat, 6 Sep 2014 01:15:36 +0000 (UTC) Received: from h2.funkthat.com (localhost [127.0.0.1]) by h2.funkthat.com (8.14.3/8.14.3) with ESMTP id s861FQpe027465 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 5 Sep 2014 18:15:26 -0700 (PDT) (envelope-from jmg@h2.funkthat.com) Received: (from jmg@localhost) by h2.funkthat.com (8.14.3/8.14.3/Submit) id s861FQj0027464; Fri, 5 Sep 2014 18:15:26 -0700 (PDT) (envelope-from jmg) Date: Fri, 5 Sep 2014 18:15:26 -0700 From: John-Mark Gurney To: Adrian Chadd Subject: Re: Cubieboard: Spurious interrupt detected Message-ID: <20140906011526.GT82175@funkthat.com> Mail-Followup-To: Adrian Chadd , Ian Lepore , "freebsd-arm@freebsd.org" , ticso@cicely.de References: <2279481.3MX4OEDuCl@quad> <20140905215702.GL3196@cicely7.cicely.de> <1409958716.1150.321.camel@revolution.hippie.lan> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.3i X-Operating-System: FreeBSD 7.2-RELEASE i386 X-PGP-Fingerprint: 54BA 873B 6515 3F10 9E88 9322 9CB1 8F74 6D3F A396 X-Files: The truth is out there X-URL: http://resnet.uoregon.edu/~gurney_j/ X-Resume: http://resnet.uoregon.edu/~gurney_j/resume.html X-TipJar: bitcoin:13Qmb6AeTgQecazTWph4XasEsP7nGRbAPE X-to-the-FBI-CIA-and-NSA: HI! HOW YA DOIN? can i haz chizburger? X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.2.2 (h2.funkthat.com [127.0.0.1]); Fri, 05 Sep 2014 18:15:27 -0700 (PDT) Cc: "freebsd-arm@freebsd.org" , ticso@cicely.de, Ian Lepore X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 06 Sep 2014 01:15:37 -0000 Adrian Chadd wrote this message on Fri, Sep 05, 2014 at 17:44 -0700: > On 5 September 2014 16:11, Ian Lepore wrote: > > On Fri, 2014-09-05 at 23:57 +0200, Bernd Walter wrote: > >> On Sat, Sep 06, 2014 at 01:43:23AM +0400, Maxim V FIlimonov wrote: > >> > And another problem: every now and then the kernel says something like that: > >> > Sep 5 19:22:37 kernel: Spurious interrupt detected > >> > Sep 5 19:22:37 kernel: Spurious interrupt detected > >> > Sep 5 19:23:46 last message repeated 10 times > >> > > >> > I've heard that FreeBSD happens to do that on ARM devices. What could be the > >> > problem here? > >> > >> Means something generates inetrrupts, which are not handled by a driver. > >> Could be the cause for your load problem too. > >> > > > > No, that would be stray interrupts. Spurious interrupts happen when an > > interrupt is asserted, but by time the processor asks the interrupt > > controller for the current active interrupt, it is no longer active. > > > > One way it can happen is when an interrupt handler writes to a device to > > clear a pending interrupt and that write takes a long time to complete > > because the device is on a slow bus, and the interrupt controller is on > > a faster bus. The EOI to the controller outraces the device write that > > would clear the pending interrupt condition, so the processor is > > re-interrupted, but by time it asks for the next active interrupt the > > device write has finally completed and the interrupt is no longer > > pending. > > > > That sequence used to happen a lot, and it was "fixed" by adding an > > l2cache sync (basically a "drain write buffer") just before an EOI. You > > sometimes still see an occasional spurious interrupt, but it shouldn't > > be happening multiple times per second as seen in the logging above. > > Hm, interesting. I remember your discussion about it on IRC. The > atheros code ends up working around this in the driver by doing a read > from the ISR after writing out bits to clear things, so the clear is > flushed out. > > I wonder if we should be asking all device drivers to be doing their > own ISR flushing before returning from their interrupt handlers. This is required on PCI (that you do a read to clear the posted/pending write)... So, IMO, yes, all device drivers should do the proper clearing of their writes to the ISR... -- John-Mark Gurney Voice: +1 415 225 5579 "All that I will do, has been done, All that I have, has not."