Date: Mon, 10 Aug 2015 18:46:07 GMT From: mihai@FreeBSD.org To: svn-soc-all@FreeBSD.org Subject: socsvn commit: r289537 - in soc2015/mihai/bhyve-on-arm-head/sys: arm/vmm boot/fdt/dts/arm Message-ID: <201508101846.t7AIk769077668@socsvn.freebsd.org>
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Author: mihai Date: Mon Aug 10 18:46:06 2015 New Revision: 289537 URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=289537 Log: sys: boot: fdt: dts: arm: added new fvp guest dts Added: soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm/fvp_ve-cortex_a15x1_guest.dts Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.h Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.h ============================================================================== --- soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.h Mon Aug 10 18:45:25 2015 (r289536) +++ soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.h Mon Aug 10 18:46:06 2015 (r289537) @@ -145,7 +145,7 @@ * HCR_TSC - Trap SMC instruction * HCR_TWE - Trap WFE instruction * HCR_TWI - Trap WFI instruction - * HCR_BSU_IS - + * HCR_BSU_IS - Barrier shareability upgrade * HCR_FB - Force broadcast TLB/branch predictor/ cache invalidate across ISB * HCR_AMO - Overrides the CPSR.A bit, and enables signaling by the VA bit * HCR_IMO - Overrides the CPSR.I bit, and enables signaling by the VI bit Added: soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm/fvp_ve-cortex_a15x1_guest.dts ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm/fvp_ve-cortex_a15x1_guest.dts Mon Aug 10 18:46:06 2015 (r289537) @@ -0,0 +1,100 @@ +/* + * ARM Ltd. Fast Models + * + * Versatile Express (VE) system model + * ARMCortexA15x1CT + * + * RTSM_VE_Cortex_A15x1.lisa + */ + +/dts-v1/; + +/ { + model = "FVP_VE_Cortex_A15x1"; + compatible = "arm,fvp_ve,cortex_a15x1"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x8000000>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x2c001000 0x1000>, + <0x2c002000 0x2000>, + <0x2c004000 0x2000>, + <0x2c006000 0x2000>; + }; + generic_timer { + compatible = "arm,armv7-timer"; + clock-frequency = <24000000>; + interrupts = < 29 30 27 26 >; + interrupt-parent = <&gic>; + }; + + v2m_serial0: uart@1c090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1c090000 0x1000>; + interrupt-parent=<&gic>; + interrupts = <37>; + }; + + v2m_serial1: uart@1c0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1c0a0000 0x1000>; + interrupt-parent=<&gic>; + interrupts = <38>; + }; + + v2m_serial2: uart@1c0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1c0b0000 0x1000>; + interrupt-parent=<&gic>; + interrupts = <39>; + }; + + v2m_serial3: uart@1c0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1c0c0000 0x1000>; + interrupt-parent=<&gic>; + interrupts = <40>; + }; + v2m_timer01: timer@1c110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x1c110000 0x1000>; + interrupt-parent=<&gic>; + interrupts = <34>; + }; + + v2m_timer23: timer@1c120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x1c120000 0x1000>; + interrupt-parent=<&gic>; + interrupts = <35>; + }; +}; +
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