Skip site navigation (1)Skip section navigation (2)
Date:      Thu, 29 Dec 2016 06:51:06 +0000 (UTC)
From:      Andrew Rybchenko <arybchik@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r310745 - head/sys/dev/sfxge/common
Message-ID:  <201612290651.uBT6p6Q3046242@repo.freebsd.org>

next in thread | raw e-mail | index | archive | help
Author: arybchik
Date: Thu Dec 29 06:51:06 2016
New Revision: 310745
URL: https://svnweb.freebsd.org/changeset/base/310745

Log:
  sfxge(4): make the common code retrieve the number of FATSOv2 contexts
  
  Submitted by:   Ivan Malov <Ivan.Malov at oktetlabs.ru>
  Reviewed by:    gnn
  Sponsored by:   Solarflare Communications, Inc.
  MFC after:      2 days
  Differential Revision:  https://reviews.freebsd.org/D8940

Modified:
  head/sys/dev/sfxge/common/ef10_nic.c
  head/sys/dev/sfxge/common/efx.h
  head/sys/dev/sfxge/common/siena_nic.c

Modified: head/sys/dev/sfxge/common/ef10_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/ef10_nic.c	Thu Dec 29 06:49:32 2016	(r310744)
+++ head/sys/dev/sfxge/common/ef10_nic.c	Thu Dec 29 06:51:06 2016	(r310745)
@@ -497,7 +497,8 @@ static	__checkReturn	efx_rc_t
 efx_mcdi_get_capabilities(
 	__in		efx_nic_t *enp,
 	__out		uint32_t *flagsp,
-	__out		uint32_t *flags2p)
+	__out		uint32_t *flags2p,
+	__out		uint32_t *tso2ncp)
 {
 	efx_mcdi_req_t req;
 	uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN,
@@ -525,10 +526,14 @@ efx_mcdi_get_capabilities(
 
 	*flagsp = MCDI_OUT_DWORD(req, GET_CAPABILITIES_OUT_FLAGS1);
 
-	if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)
+	if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
 		*flags2p = 0;
-	else
+		*tso2ncp = 0;
+	} else {
 		*flags2p = MCDI_OUT_DWORD(req, GET_CAPABILITIES_V2_OUT_FLAGS2);
+		*tso2ncp = MCDI_OUT_WORD(req,
+				GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
+	}
 
 	return (0);
 
@@ -963,9 +968,11 @@ ef10_get_datapath_caps(
 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 	uint32_t flags;
 	uint32_t flags2;
+	uint32_t tso2nc;
 	efx_rc_t rc;
 
-	if ((rc = efx_mcdi_get_capabilities(enp, &flags, &flags2)) != 0)
+	if ((rc = efx_mcdi_get_capabilities(enp, &flags, &flags2,
+					    &tso2nc)) != 0)
 		goto fail1;
 
 #define	CAP_FLAG(flags1, field)		\
@@ -992,6 +999,10 @@ ef10_get_datapath_caps(
 	encp->enc_fw_assisted_tso_v2_enabled =
 	    CAP_FLAG2(flags2, TX_TSO_V2) ? B_TRUE : B_FALSE;
 
+	/* Get the number of TSO contexts (FATSOv2) */
+	encp->enc_fw_assisted_tso_v2_n_contexts =
+		CAP_FLAG2(flags2, TX_TSO_V2) ? tso2nc : 0;
+
 	/* Check if the firmware has vadapter/vport/vswitch support */
 	encp->enc_datapath_cap_evb =
 	    CAP_FLAG(flags, EVB) ? B_TRUE : B_FALSE;

Modified: head/sys/dev/sfxge/common/efx.h
==============================================================================
--- head/sys/dev/sfxge/common/efx.h	Thu Dec 29 06:49:32 2016	(r310744)
+++ head/sys/dev/sfxge/common/efx.h	Thu Dec 29 06:51:06 2016	(r310745)
@@ -1139,6 +1139,8 @@ typedef struct efx_nic_cfg_s {
 	uint32_t		enc_tx_tso_tcp_header_offset_limit;
 	boolean_t		enc_fw_assisted_tso_enabled;
 	boolean_t		enc_fw_assisted_tso_v2_enabled;
+	/* Number of TSO contexts on the NIC (FATSOv2) */
+	uint32_t		enc_fw_assisted_tso_v2_n_contexts;
 	boolean_t		enc_hw_tx_insert_vlan_enabled;
 	/* Datapath firmware vadapter/vport/vswitch support */
 	boolean_t		enc_datapath_cap_evb;

Modified: head/sys/dev/sfxge/common/siena_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/siena_nic.c	Thu Dec 29 06:49:32 2016	(r310744)
+++ head/sys/dev/sfxge/common/siena_nic.c	Thu Dec 29 06:51:06 2016	(r310745)
@@ -152,6 +152,7 @@ siena_board_cfg(
 	encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
 	encp->enc_fw_assisted_tso_enabled = B_FALSE;
 	encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
+	encp->enc_fw_assisted_tso_v2_n_contexts = 0;
 	encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
 
 	/* Siena supports two 10G ports, and 8 lanes of PCIe Gen2 */



Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201612290651.uBT6p6Q3046242>