Date: Tue, 17 Sep 2002 02:08:17 -0700 (PDT) From: Don Lewis <dl-freebsd@catspoiler.org> To: brandt@fokus.gmd.de Cc: phk@critter.freebsd.dk, archie@dellroad.org, bde@zeta.org.au, joe@FreeBSD.org, obrien@FreeBSD.org, cvs-committers@FreeBSD.org, cvs-all@FreeBSD.org Subject: Re: cvs commit: src/sys/kern kern_timeout.c Message-ID: <200209170908.g8H98Hwr015356@gw.catspoiler.org> In-Reply-To: <20020917100940.U812-200000@beagle.fokus.gmd.de>
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On 17 Sep, Harti Brandt wrote: > > Hi, > > I just took the opportunity and to analyze the xl_mii_readreg routine that > is one of the timeout hogs (through mii_tick). Instead of making DELAY(1) > to do the right thing (which seems a rather complex task) I tried to find > a local solution and did the following: The MII interface my be local to a chip, it may connect two chips on a card, or it may connect a card to an external device through a connector and cable. This interface is used to send the transmit and receive data between the Ethernet MAC and PHY devices, as well as to communicate management (control and status) information. The management information is sent over a one bit bidirectional data bus that has a separate clock signal to indicate when each bit of data is on the bus. Many implementations rely on the host processor to send the management data across this bus by fiddling with a control register to wiggle (and sense) the clock and data signals. The IEEE 802.3 standard specifies the timing of the clock and data lines. Some implementations of the MII bus can run much faster than the standard, but I don't know the timing requirements of the cards targeted by this driver. > (1) replaced all calls to DELAY(1) with a bus_space_read_4() on a card > address. Because there are 184 DELAY(1) calls in each xl_mii_readreg each > of which takes a mean of 8.5usecs this cuts down the overall time from > 1.8msec to around 320usecs. I think we're probably ok here. The standard says the minimum high and low times for the clock signal are 160ns, with a minimum clock period of 400ns. If I do the math correctly, your scheme wiggles something about every 1.7us. > (2) two macros MII_SET and MII_CLR are used to fiddle with the MDIO bits. > This looks fine from an aesthetic standpoint of view, but adds some dozens > of additional operations. I introduced a MII_SETCLR macro which can set > and clear bits at the same time. This reduces the readreg time further to > 250usecs. There is a problem here. The 802.3 spec says that MDIO may not change within 10ns of the rising edge of the clock. Even if the card doesn't require strict adherence to the 802.3 timing, I'd expect that changing both at the same time would be hazardous. > Because each mii_tick takes approx. 4 readregs this is still a lot, but > better than before. Perhaps you could have a look at the patch that I have > attached. > > Regards, > harti To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe cvs-all" in the body of the message
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