From owner-svn-src-all@FreeBSD.ORG Thu Nov 26 15:11:19 2009 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id A22F8106568D; Thu, 26 Nov 2009 15:11:19 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 779038FC18; Thu, 26 Nov 2009 15:11:19 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id nAQFBJLH085659; Thu, 26 Nov 2009 15:11:19 GMT (envelope-from mav@svn.freebsd.org) Received: (from mav@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id nAQFBJeY085657; Thu, 26 Nov 2009 15:11:19 GMT (envelope-from mav@svn.freebsd.org) Message-Id: <200911261511.nAQFBJeY085657@svn.freebsd.org> From: Alexander Motin Date: Thu, 26 Nov 2009 15:11:19 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org X-SVN-Group: stable-8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r199834 - stable/8/sys/i386/cpufreq X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Nov 2009 15:11:19 -0000 Author: mav Date: Thu Nov 26 15:11:19 2009 New Revision: 199834 URL: http://svn.freebsd.org/changeset/base/199834 Log: MFC r199268, r199269, r199273: Core2Duo/Core2Quad CPUs are unable to control frequency of single CPU core, only pair of them. As result, both cores are running on highest one of requested frequencies, and that is reported by status register. Such behavior confuses frequency validation logic, as it runs on only one core, as SMP is not yet launched, making EIST completely unusable. Disable frequency validation by default, for systems with more then one CPU, until we can implement it properly. It looks like making more harm now then benefits. Add 'hw.est.strict' loader tunable to control it. PR: amd64/140506 Modified: stable/8/sys/i386/cpufreq/est.c Directory Properties: stable/8/sys/ (props changed) stable/8/sys/amd64/include/xen/ (props changed) stable/8/sys/cddl/contrib/opensolaris/ (props changed) stable/8/sys/contrib/dev/acpica/ (props changed) stable/8/sys/contrib/pf/ (props changed) stable/8/sys/dev/xen/xenpci/ (props changed) Modified: stable/8/sys/i386/cpufreq/est.c ============================================================================== --- stable/8/sys/i386/cpufreq/est.c Thu Nov 26 14:56:58 2009 (r199833) +++ stable/8/sys/i386/cpufreq/est.c Thu Nov 26 15:11:19 2009 (r199834) @@ -96,6 +96,8 @@ struct est_softc { static int msr_info_enabled = 0; TUNABLE_INT("hw.est.msr_info", &msr_info_enabled); +static int strict = -1; +TUNABLE_INT("hw.est.strict", &strict); /* Default bus clock value for Centrino processors. */ #define INTEL_BUS_CLK 100 @@ -1025,6 +1027,9 @@ est_attach(device_t dev) sc = device_get_softc(dev); sc->dev = dev; + /* On SMP system we can't guarantie independent freq setting. */ + if (strict == -1 && mp_ncpus > 1) + strict = 0; /* Check CPU for supported settings. */ if (est_get_info(dev)) return (ENXIO); @@ -1119,17 +1124,21 @@ est_acpi_info(device_t dev, freq_info ** */ if (sets[i].freq > 0) { error = est_set_id16(dev, sets[i].spec[0], 1); - if (error != 0) { + if (error != 0 && strict) { if (bootverbose) device_printf(dev, "Invalid freq %u, " "ignored.\n", sets[i].freq); - } else { - table[j].freq = sets[i].freq; - table[j].volts = sets[i].volts; - table[j].id16 = sets[i].spec[0]; - table[j].power = sets[i].power; - ++j; + continue; + } else if (error != 0 && bootverbose) { + device_printf(dev, "Can't check freq %u, " + "it may be invalid\n", + sets[i].freq); } + table[j].freq = sets[i].freq; + table[j].volts = sets[i].volts; + table[j].id16 = sets[i].spec[0]; + table[j].power = sets[i].power; + ++j; } } /* restore saved setting */