Date: Tue, 17 Sep 2002 11:19:55 +0200 (CEST) From: Harti Brandt <brandt@fokus.gmd.de> To: Don Lewis <dl-freebsd@catspoiler.org> Cc: brandt@fokus.gmd.de, <phk@critter.freebsd.dk>, <archie@dellroad.org>, <bde@zeta.org.au>, <joe@FreeBSD.org>, <obrien@FreeBSD.org>, <cvs-committers@FreeBSD.org>, <cvs-all@FreeBSD.org> Subject: Re: cvs commit: src/sys/kern kern_timeout.c Message-ID: <20020917111410.U812-100000@beagle.fokus.gmd.de> In-Reply-To: <200209170908.g8H98Hwr015356@gw.catspoiler.org>
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On Tue, 17 Sep 2002, Don Lewis wrote: DL>On 17 Sep, Harti Brandt wrote: DL>> DL>> Hi, DL>> DL>> I just took the opportunity and to analyze the xl_mii_readreg routine that DL>> is one of the timeout hogs (through mii_tick). Instead of making DELAY(1) DL>> to do the right thing (which seems a rather complex task) I tried to find DL>> a local solution and did the following: DL> DL>The MII interface my be local to a chip, it may connect two chips on a DL>card, or it may connect a card to an external device through a connector DL>and cable. This interface is used to send the transmit and receive data DL>between the Ethernet MAC and PHY devices, as well as to communicate DL>management (control and status) information. The management information DL>is sent over a one bit bidirectional data bus that has a separate clock DL>signal to indicate when each bit of data is on the bus. Many DL>implementations rely on the host processor to send the management data DL>across this bus by fiddling with a control register to wiggle (and DL>sense) the clock and data signals. The IEEE 802.3 standard specifies DL>the timing of the clock and data lines. Some implementations of the MII DL>bus can run much faster than the standard, but I don't know the timing DL>requirements of the cards targeted by this driver. I have the standard here. The driver has two macros: MII_SET and MII_CLR. Both of them read the card register (bus_space_read_2), set or clear some bits and write the value back. According to the DELAY() discussion in january and a comment in the Linux driver the input operation between two output operation is enough to get the timing correct. DL>> (2) two macros MII_SET and MII_CLR are used to fiddle with the MDIO bits. DL>> This looks fine from an aesthetic standpoint of view, but adds some dozens DL>> of additional operations. I introduced a MII_SETCLR macro which can set DL>> and clear bits at the same time. This reduces the readreg time further to DL>> 250usecs. DL> DL>There is a problem here. The 802.3 spec says that MDIO may not change DL>within 10ns of the rising edge of the clock. Even if the card doesn't DL>require strict adherence to the 802.3 timing, I'd expect that changing DL>both at the same time would be hazardous. In the place where the macro is used, it clears the clock bit and sets the data bit, so this is the falling edge of the clock, which should be ok. harti -- harti brandt, http://www.fokus.gmd.de/research/cc/cats/employees/hartmut.brandt/private brandt@fokus.gmd.de, brandt@fokus.fhg.de To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe cvs-all" in the body of the message
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