From owner-freebsd-smp Sun Jul 1 7: 7:39 2001 Delivered-To: freebsd-smp@freebsd.org Received: from srv1.cosmo-project.de (srv1.cosmo-project.de [213.83.6.106]) by hub.freebsd.org (Postfix) with ESMTP id 8605137B403; Sun, 1 Jul 2001 07:07:31 -0700 (PDT) (envelope-from ticso@mail.cicely.de) Received: from mail.cicely.de (cicely20 [10.1.1.22]) by srv1.cosmo-project.de (8.11.0/8.11.0) with ESMTP id f61E7H672239; Sun, 1 Jul 2001 16:07:19 +0200 (CEST) Received: (from ticso@localhost) by mail.cicely.de (8.11.0/8.11.0) id f61E7it22706; Sun, 1 Jul 2001 16:07:44 +0200 (CEST) Date: Sun, 1 Jul 2001 16:07:38 +0200 From: Bernd Walter To: Valentin Nechayev Cc: "E.B. Dreger" , Bernd Walter , freebsd-smp@FreeBSD.ORG, freebsd-hackers@FreeBSD.ORG Subject: Re: libc_r locking... why? Message-ID: <20010701160738.A22683@cicely20.cicely.de> References: <20010629211818.A17309@cicely20.cicely.de> <20010701155256.C376@iv.nn.kiev.ua> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5i In-Reply-To: <20010701155256.C376@iv.nn.kiev.ua>; from netch@iv.nn.kiev.ua on Sun, Jul 01, 2001 at 03:52:56PM +0300 Sender: owner-freebsd-smp@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.org On Sun, Jul 01, 2001 at 03:52:56PM +0300, Valentin Nechayev wrote: > Fri, Jun 29, 2001 at 19:56:40, eddy+public+spam (E.B. Dreger) wrote about "Re: libc_r locking... why?": > > > > A Token may not be enough because writes may be reordered. > > AFAIK it's false for i386 architecture. Please correct me if needed. In -currents NOTEs I found this: # CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables # reorder). This option should not be used if you use memory mapped # I/O device(s). A good sign that it may be at least possible on some CPUs. OK that's not an MP capable CPU. What you need is an x86 guru or asume worst which will be the best thing anyway - otherwise you can't use it on other machines and sometimes programms get very old. I also don't know what the following is: # CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD # K5/K6/K6-2 cpus. > > Here is where I want to learn more about cache coherency, inter-processor > > interrupts, and APIC programming. I'd imagine that the latter two are > > lower-level than I'd be using, but I still want to know the "how and why" > > beneath the scenes. > > Did you try to read MP chipsets white papers? I can't say very much about coherency problems on x86 but I can say for shure that you have to worry about this on every other MP platform including IA64. -- B.Walter COSMO-Project http://www.cosmo-project.de ticso@cicely.de Usergroup info@cosmo-project.de To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-smp" in the body of the message