Date: Tue, 29 Jan 2008 20:01:09 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 134408 for review Message-ID: <200801292001.m0TK19j1004828@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=134408 Change 134408 by imp@imp_lighthouse on 2008/01/29 20:00:49 We need to read the CPU id on octeons. Move setting the cause register to zero to be done always. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/locore.S#21 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/locore.S#21 (text+ko) ==== @@ -101,6 +101,8 @@ ASM_ENTRY(_start) VECTOR(_locore, unknown) /* UNSAFE TO USE a0..a3, since some bootloaders pass that to us */ + mtc0 zero, COP_0_CAUSE_REG # Clear soft interrupts + #if defined(TARGET_OCTEON) /* * t1: Bits to set explicitly: @@ -113,8 +115,6 @@ /* Reset these bits */ li t0, ~(MIPS_SR_DE | MIPS_SR_SOFT_RESET | MIPS_SR_ERL | MIPS_SR_EXL | MIPS_SR_INT_IE) #else - mtc0 zero, COP_0_CAUSE_REG # Clear soft interrupts - /* * t0: Bits to preserve if set: * Soft reset @@ -137,7 +137,6 @@ or t2, t1 mtc0 t2, COP_0_STATUS_REG COP0_SYNC - /* Make sure KSEG0 is cached */ li t0, CFG_K0_CACHED mtc0 t0, MIPS_COP_0_CONFIG @@ -219,7 +218,14 @@ #endif +#if defined(TARGET_OCTEON) /* Maybe this is mips32/64 generic? */ + .set push + .set mips32r2 + rdhwr t0, $0 + .set pop +#else move t0, zero +#endif /* Stage the secondary cpu start until later */ bne t0, zero, start_secondary
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