Date: Mon, 4 Aug 2008 17:47:50 GMT From: Sam Leffler <sam@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 146640 for review Message-ID: <200808041747.m74HloQU091705@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=146640 Change 146640 by sam@sam_ebb on 2008/08/04 17:47:03 0.10.5.10 Affected files ... .. //depot/projects/vap/sys/contrib/dev/ath/COPYRIGHT#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/README#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/ah_desc.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/ah_devid.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/ah_soc.h#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/alpha-elf.hal.o.uu#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/alpha-elf.inc#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/alpha-elf.opt_ah.h#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/ap30.hal.o.uu#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/ap30.inc#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/ap30.opt_ah.h#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/ap43.hal.o.uu#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/ap43.inc#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/ap43.opt_ah.h#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/ap51.hal.o.uu#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/ap51.inc#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/ap51.opt_ah.h#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/ap61.hal.o.uu#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/ap61.inc#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/ap61.opt_ah.h#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/arm9-le-thumb-elf.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/arm9-le-thumb-elf.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/arm9-le-thumb-elf.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/armv4-be-elf.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/armv4-be-elf.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/armv4-be-elf.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/armv4-le-elf.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/armv4-le-elf.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/armv4-le-elf.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/i386-elf.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/i386-elf.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/i386-elf.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mips-be-elf.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mips-be-elf.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mips-be-elf.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mips-le-elf.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mips-le-elf.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mips-le-elf.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mips1-be-elf.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mips1-be-elf.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mips1-be-elf.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mips1-le-elf.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mips1-le-elf.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mips1-le-elf.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mipsisa32-be-elf.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mipsisa32-be-elf.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mipsisa32-be-elf.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mipsisa32-le-elf.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mipsisa32-le-elf.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/mipsisa32-le-elf.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/powerpc-be-eabi.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/powerpc-be-eabi.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/powerpc-be-eabi.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/powerpc-be-elf.hal.o.uu#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/powerpc-be-elf.inc#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/powerpc-be-elf.opt_ah.h#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/powerpc-le-eabi.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/powerpc-le-eabi.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/powerpc-le-eabi.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/sh4-le-elf.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/sh4-le-elf.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/sh4-le-elf.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/sparc-be-elf.hal.o.uu#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/sparc-be-elf.inc#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/sparc-be-elf.opt_ah.h#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/sparc64-be-elf.hal.o.uu#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/sparc64-be-elf.inc#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/sparc64-be-elf.opt_ah.h#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/wackelf.c#3 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/x86_64-elf.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/x86_64-elf.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/x86_64-elf.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/xscale-be-elf.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/xscale-be-elf.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/xscale-be-elf.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/xscale-le-elf.hal.o.uu#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/xscale-le-elf.inc#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/public/xscale-le-elf.opt_ah.h#5 edit .. //depot/projects/vap/sys/contrib/dev/ath/version.h#5 edit Differences ... ==== //depot/projects/vap/sys/contrib/dev/ath/COPYRIGHT#5 (text+ko) ==== @@ -4,7 +4,7 @@ redistribution with changes. /*- - * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting, Atheros * Communications, Inc. All rights reserved. * * Redistribution and use in source and binary forms are permitted @@ -38,5 +38,5 @@ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGES. * - * $Id: //depot/sw/branches/sam_hal/COPYRIGHT#1 $ + * $Id: //depot/sw/branches/sam_hal/COPYRIGHT#2 $ */ ==== //depot/projects/vap/sys/contrib/dev/ath/README#5 (text+ko) ==== @@ -1,11 +1,11 @@ -$Id: //depot/sw/branches/sam_hal/README#2 $ +$Id: //depot/sw/branches/sam_hal/README#3 $ Atheros Hardware Access Layer (HAL) =================================== -* Copyright (c) 2002-2006 Sam Leffler. -* Copyright (c) 2002-2006 Atheros Communications, Inc. +* Copyright (c) 2002-2008 Sam Leffler. +* Copyright (c) 2002-2008 Atheros Communications, Inc. * All rights reserved. Read the file COPYRIGHT for the complete copyright. ==== //depot/projects/vap/sys/contrib/dev/ath/ah.h#5 (text+ko) ==== @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting, Atheros * Communications, Inc. All rights reserved. * * Redistribution and use in source and binary forms are permitted @@ -33,7 +33,7 @@ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGES. * - * $Id: //depot/sw/branches/sam_hal/ah.h#19 $ + * $Id: //depot/sw/branches/sam_hal/ah.h#32 $ */ #ifndef _ATH_AH_H_ @@ -132,6 +132,9 @@ HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ HAL_CAP_INTMIT = 29, /* interference mitigation */ HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */ + HAL_CAP_HT = 31, /* hardware can support HT */ + HAL_CAP_NUMTXCHAIN = 32, /* # TX chains supported */ + HAL_CAP_NUMRXCHAIN = 33, /* # RX chains supported */ HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */ } HAL_CAPABILITY_TYPE; @@ -304,7 +307,8 @@ HAL_PKT_TYPE_BEACON = 3, HAL_PKT_TYPE_PROBE_RESP = 4, HAL_PKT_TYPE_CHIRP = 5, - HAL_PKT_TYPE_GRP_POLL = 6, + HAL_PKT_TYPE_GRP_POLL = 6, + HAL_PKT_TYPE_AMPDU = 7, } HAL_PKT_TYPE; /* Rx Filter Frame Types */ @@ -318,7 +322,8 @@ HAL_RX_FILTER_XRPOLL = 0x00000040, /* Allow XR poll frmae */ HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ - HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors*/ + HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors */ + HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ } HAL_RX_FILTER; typedef enum { @@ -357,6 +362,8 @@ HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ HAL_INT_GPIO = 0x01000000, HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ + HAL_INT_CST = 0x10000000, /* Non-common mapping */ + HAL_INT_GTT = 0x20000000, /* Non-common mapping */ HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ HAL_INT_BMISC = HAL_INT_TIM @@ -389,8 +396,8 @@ * Channels are specified by frequency. */ typedef struct { + u_int32_t channelFlags; /* see below */ u_int16_t channel; /* setting in Mhz */ - u_int16_t channelFlags; /* see below */ u_int8_t privFlags; int8_t maxRegTxPower; /* max regulatory tx power in dBm */ int8_t maxTxPower; /* max true tx power in 0.5 dBm */ @@ -398,18 +405,21 @@ } HAL_CHANNEL; /* channelFlags */ -#define CHANNEL_CW_INT 0x0002 /* CW interference detected on channel */ -#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ -#define CHANNEL_CCK 0x0020 /* CCK channel */ -#define CHANNEL_OFDM 0x0040 /* OFDM channel */ -#define CHANNEL_2GHZ 0x0080 /* 2 GHz spectrum channel. */ -#define CHANNEL_5GHZ 0x0100 /* 5 GHz spectrum channel */ -#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */ -#define CHANNEL_DYN 0x0400 /* dynamic CCK-OFDM channel */ -#define CHANNEL_XR 0x0800 /* XR channel */ -#define CHANNEL_STURBO 0x2000 /* Static turbo, no 11a-only usage */ -#define CHANNEL_HALF 0x4000 /* Half rate channel */ -#define CHANNEL_QUARTER 0x8000 /* Quarter rate channel */ +#define CHANNEL_CW_INT 0x00002 /* CW interference detected on channel */ +#define CHANNEL_TURBO 0x00010 /* Turbo Channel */ +#define CHANNEL_CCK 0x00020 /* CCK channel */ +#define CHANNEL_OFDM 0x00040 /* OFDM channel */ +#define CHANNEL_2GHZ 0x00080 /* 2 GHz spectrum channel */ +#define CHANNEL_5GHZ 0x00100 /* 5 GHz spectrum channel */ +#define CHANNEL_PASSIVE 0x00200 /* Only passive scan allowed in the channel */ +#define CHANNEL_DYN 0x00400 /* dynamic CCK-OFDM channel */ +#define CHANNEL_XR 0x00800 /* XR channel */ +#define CHANNEL_STURBO 0x02000 /* Static turbo, no 11a-only usage */ +#define CHANNEL_HALF 0x04000 /* Half rate channel */ +#define CHANNEL_QUARTER 0x08000 /* Quarter rate channel */ +#define CHANNEL_HT20 0x10000 /* 11n 20MHZ channel */ +#define CHANNEL_HT40PLUS 0x20000 /* 11n 40MHZ channel w/ ext chan above */ +#define CHANNEL_HT40MINUS 0x40000 /* 11n 40MHZ channel w/ ext chan below */ /* privFlags */ #define CHANNEL_INTERFERENCE 0x01 /* Software use: channel interference @@ -432,8 +442,15 @@ #define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) #define CHANNEL_108A CHANNEL_T #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) +#define CHANNEL_G_HT20 (CHANNEL_G|CHANNEL_HT20) +#define CHANNEL_A_HT20 (CHANNEL_A|CHANNEL_HT20) +#define CHANNEL_G_HT40PLUS (CHANNEL_G|CHANNEL_HT40PLUS) +#define CHANNEL_G_HT40MINUS (CHANNEL_G|CHANNEL_HT40MINUS) +#define CHANNEL_A_HT40PLUS (CHANNEL_A|CHANNEL_HT40PLUS) +#define CHANNEL_A_HT40MINUS (CHANNEL_A|CHANNEL_HT40MINUS) #define CHANNEL_ALL \ - (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ | CHANNEL_5GHZ | CHANNEL_TURBO) + (CHANNEL_OFDM | CHANNEL_CCK| CHANNEL_2GHZ | CHANNEL_5GHZ | \ + CHANNEL_TURBO | CHANNEL_HT20 | CHANNEL_HT40PLUS | CHANNEL_HT40MINUS) #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) #define HAL_ANTENNA_MIN_MODE 0 @@ -472,16 +489,22 @@ HAL_MODE_XR = 0x100, /* XR channels */ HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */ HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */ - HAL_MODE_ALL = 0xfff + HAL_MODE_11NG_HT20 = 0x008000, + HAL_MODE_11NA_HT20 = 0x010000, + HAL_MODE_11NG_HT40PLUS = 0x020000, + HAL_MODE_11NG_HT40MINUS = 0x040000, + HAL_MODE_11NA_HT40PLUS = 0x080000, + HAL_MODE_11NA_HT40MINUS = 0x100000, + HAL_MODE_ALL = 0xffffff }; typedef struct { int rateCount; /* NB: for proper padding */ - u_int8_t rateCodeToIndex[32]; /* back mapping */ + u_int8_t rateCodeToIndex[144]; /* back mapping */ struct { u_int8_t valid; /* valid for rate control use */ u_int8_t phy; /* CCK/OFDM/XR */ - u_int16_t rateKbps; /* transfer rate in kbs */ + u_int32_t rateKbps; /* transfer rate in kbs */ u_int8_t rateCode; /* rate for h/w descriptors */ u_int8_t shortPreamble; /* mask for enabling short * preamble in CCK rate code */ @@ -500,6 +523,46 @@ } HAL_RATE_SET; /* + * 802.11n specific structures and enums + */ +typedef enum { + HAL_CHAINTYPE_TX = 1, /* Tx chain type */ + HAL_CHAINTYPE_RX = 2, /* RX chain type */ +} HAL_CHAIN_TYPE; + +typedef struct { + u_int Tries; + u_int Rate; + u_int PktDuration; + u_int ChSel; + u_int RateFlags; +#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ +#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ +#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ +} HAL_11N_RATE_SERIES; + +typedef enum { + HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ + HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ +} HAL_HT_MACMODE; + +typedef enum { + HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ + HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ +} HAL_HT_PHYMODE; + +typedef enum { + HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ + HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ +} HAL_HT_EXTPROTSPACING; + + +typedef enum { + HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ + HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ +} HAL_HT_RXCLEAR; + +/* * Antenna switch control. By default antenna selection * enables multiple (2) antenna use. To force use of the * A or B antenna only specify a fixed setting. Fixing @@ -569,7 +632,7 @@ /* * Like HAL_BEACON_STATE but for non-station mode setup. - * NB: see above flag definitions + * NB: see above flag definitions for bt_intval. */ typedef struct { u_int32_t bt_intval; /* beacon interval+flags */ @@ -577,6 +640,10 @@ u_int32_t bt_nextatim; /* next ATIM in TU */ u_int32_t bt_nextdba; /* next DBA in 1/8th TU */ u_int32_t bt_nextswba; /* next SWBA in 1/8th TU */ + u_int32_t bt_flags; /* timer enables */ +#define HAL_BEACON_TBTT_EN 0x00000001 +#define HAL_BEACON_DBA_EN 0x00000002 +#define HAL_BEACON_SWBA_EN 0x00000004 } HAL_BEACON_TIMERS; /* @@ -608,7 +675,7 @@ struct ath_hal { u_int32_t ah_magic; /* consistency check magic number */ u_int32_t ah_abi; /* HAL ABI version */ -#define HAL_ABI_VERSION 0x06102600 /* YYMMDDnn */ +#define HAL_ABI_VERSION 0x08060800 /* YYMMDDnn */ u_int16_t ah_devid; /* PCI device ID */ u_int16_t ah_subvendorid; /* PCI subvendor ID */ HAL_SOFTC ah_sc; /* back pointer to driver/os state */ @@ -739,6 +806,8 @@ HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, HAL_ANT_SETTING); + HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); + u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); @@ -767,7 +836,6 @@ HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, HAL_CHANNEL *); - /* Beacon Management Functions */ void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, const HAL_BEACON_TIMERS *); @@ -811,9 +879,7 @@ /* * Set the Vendor ID for Vendor SKU's which can modify the * channel properties returned by ath_hal_init_channels. - * Return AH_TRUE if set succeeds */ - extern HAL_BOOL __ahdecl ath_hal_setvendor(struct ath_hal *, u_int32_t ); /* @@ -830,7 +896,7 @@ extern HAL_BOOL __ahdecl ath_hal_init_channels(struct ath_hal *, HAL_CHANNEL *chans, u_int maxchans, u_int *nchans, u_int8_t *regclassids, u_int maxregids, u_int *nregids, - HAL_CTRY_CODE cc, u_int16_t modeSelect, + HAL_CTRY_CODE cc, u_int modeSelect, HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels); /* @@ -845,12 +911,6 @@ extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*, HAL_CTRY_CODE); /* - * Return rate table for specified mode (11a, 11b, 11g, etc). - */ -extern const HAL_RATE_TABLE * __ahdecl ath_hal_getratetable(struct ath_hal *, - u_int mode); - -/* * Calculate the transmit duration of a frame. */ extern u_int16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, @@ -863,6 +923,11 @@ extern HAL_BOOL __ahdecl ath_hal_ispublicsafetysku(struct ath_hal *); /* + * Return if device is operating in 900 MHz band. + */ +extern HAL_BOOL ath_hal_isgsmsku(struct ath_hal *); + +/* * Convert between IEEE channel number and channel frequency * using the specified channel flags; e.g. CHANNEL_2GHZ. */ ==== //depot/projects/vap/sys/contrib/dev/ath/ah_desc.h#5 (text+ko) ==== @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting, Atheros * Communications, Inc. All rights reserved. * * Redistribution and use in source and binary forms are permitted @@ -33,12 +33,14 @@ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGES. * - * $Id: //depot/sw/branches/sam_hal/ah_desc.h#5 $ + * $Id: //depot/sw/branches/sam_hal/ah_desc.h#8 $ */ #ifndef _DEV_ATH_DESC_H #define _DEV_ATH_DESC_H +#include "opt_ah.h" /* NB: required for AH_SUPPORT_AR5416 */ + /* * Transmit descriptor status. This structure is filled * in only after the tx descriptor process method finds a @@ -60,11 +62,32 @@ u_int8_t ts_virtcol; /* virtual collision count */ u_int8_t ts_antenna; /* antenna information */ u_int8_t ts_finaltsi; /* final transmit series index */ +#ifdef AH_SUPPORT_AR5416 + /* 802.11n status */ + u_int8_t ts_flags; /* misc flags */ + int8_t ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */ + int8_t ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */ +/* #define ts_rssi ts_rssi_combined */ + u_int32_t ts_ba_low; /* blockack bitmap low */ + u_int32_t ts_ba_high; /* blockack bitmap high */ + u_int32_t ts_evm0; /* evm bytes */ + u_int32_t ts_evm1; + u_int32_t ts_evm2; +#endif /* AH_SUPPORT_AR5416 */ }; +/* bits found in ts_status */ #define HAL_TXERR_XRETRY 0x01 /* excessive retries */ #define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */ #define HAL_TXERR_FIFO 0x04 /* fifo underrun */ +#define HAL_TXERR_XTXOP 0x08 /* txop exceeded */ +#define HAL_TXERR_DESC_CFG_ERR 0x10 /* Error in 20/40 desc config */ +#define HAL_TXERR_DATA_UNDERRUN 0x20 /* Tx buffer underrun */ +#define HAL_TXERR_DELIM_UNDERRUN 0x40 /* Tx delimiter underrun */ + +/* bits found in ts_flags */ +#define HAL_TX_BA 0x01 /* Block Ack seen */ +#define HAL_TX_AGGR 0x02 /* Aggregate */ /* * Receive descriptor status. This structure is filled @@ -79,7 +102,9 @@ * for some errors (e.g. a decryption error), it may be meaningful. * * Note that the receive timestamp is expanded using the TSF to - * 15 bits (regardless of what the h/w provides directly). + * at least 15 bits (regardless of what the h/w provides directly). + * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to + * find out if the hardware is capable. * * rx_rssi is in units of dbm above the noise floor. This value * is measured during the preamble and PLCP; i.e. with the initial @@ -88,22 +113,45 @@ */ struct ath_rx_status { u_int16_t rs_datalen; /* rx frame length */ - u_int16_t rs_tstamp; /* h/w assigned timestamp */ u_int8_t rs_status; /* rx status, 0 => recv ok */ u_int8_t rs_phyerr; /* phy error code */ - int8_t rs_rssi; /* rx frame RSSI */ + int8_t rs_rssi; /* rx frame RSSI (combined for 11n) */ u_int8_t rs_keyix; /* key cache index */ u_int8_t rs_rate; /* h/w receive rate index */ - u_int8_t rs_antenna; /* antenna information */ u_int8_t rs_more; /* more descriptors follow */ + u_int32_t rs_tstamp; /* h/w assigned timestamp */ + u_int32_t rs_antenna; /* antenna information */ +#ifdef AH_SUPPORT_AR5416 + /* 802.11n status */ + int8_t rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */ + int8_t rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */ + u_int8_t rs_isaggr; /* is part of the aggregate */ + u_int8_t rs_moreaggr; /* more frames in aggr to follow */ + u_int8_t rs_num_delims; /* number of delims in aggr */ + u_int8_t rs_flags; /* misc flags */ + u_int32_t rs_evm0; /* evm bytes */ + u_int32_t rs_evm1; + u_int32_t rs_evm2; +#endif /* AH_SUPPORT_AR5416 */ }; +/* bits found in rs_status */ #define HAL_RXERR_CRC 0x01 /* CRC error on frame */ #define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */ #define HAL_RXERR_FIFO 0x04 /* fifo overrun */ #define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */ #define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */ +/* bits found in rs_flags */ +#define HAL_RX_MORE 0x01 /* more descriptors follow */ +#define HAL_RX_MORE_AGGR 0x02 /* more frames in aggr */ +#define HAL_RX_GI 0x04 /* full gi */ +#define HAL_RX_2040 0x08 /* 40 Mhz */ +#define HAL_RX_DELIM_CRC_PRE 0x10 /* crc error in delimiter pre */ +#define HAL_RX_DELIM_CRC_POST 0x20 /* crc error in delim after */ +#define HAL_RX_DECRYPT_BUSY 0x40 /* decrypt was too slow */ +#define HAL_RX_DUP_FRAME 0x80 /* Dup frame rx'd on control channel */ + enum { HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */ HAL_PHYERR_TIMING = 1, /* Timing error */ @@ -143,6 +191,12 @@ * to complete the work. Status for completed frames is returned * in a device-independent format. */ +#ifdef AH_SUPPORT_AR5416 +#define HAL_DESC_HW_SIZE 20 +#else +#define HAL_DESC_HW_SIZE 4 +#endif /* AH_SUPPORT_AR5416 */ + struct ath_desc { /* * The following definitions are passed directly @@ -153,7 +207,7 @@ u_int32_t ds_data; /* phys address of data buffer */ u_int32_t ds_ctl0; /* opaque DMA control 0 */ u_int32_t ds_ctl1; /* opaque DMA control 1 */ - u_int32_t ds_hw[4]; /* opaque h/w region */ + u_int32_t ds_hw[HAL_DESC_HW_SIZE]; /* opaque h/w region */ }; struct ath_desc_status { @@ -175,6 +229,9 @@ #define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */ /* NB: this only affects frame, not any RTS/CTS */ #define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */ +#define HAL_TXDESC_EXT_ONLY 0x0080 /* send on ext channel only (11n) */ +#define HAL_TXDESC_EXT_AND_CTL 0x0100 /* send on ext + ctl channels (11n) */ +#define HAL_TXDESC_VMF 0x0200 /* virtual more frag */ /* flags passed to rx descriptor setup methods */ #define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */ ==== //depot/projects/vap/sys/contrib/dev/ath/ah_devid.h#5 (text+ko) ==== @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting, Atheros * Communications, Inc. All rights reserved. * * Redistribution and use in source and binary forms are permitted @@ -33,7 +33,7 @@ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGES. * - * $Id: //depot/sw/branches/sam_hal/ah_devid.h#2 $ + * $Id: //depot/sw/branches/sam_hal/ah_devid.h#5 $ */ #ifndef _DEV_ATH_DEVID_H_ @@ -70,7 +70,8 @@ #define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */ #define AR5212_AR2315_REV6 0x0086 /* AR2315 WMAC (AP51-Light) */ #define AR5212_AR2315_REV7 0x0087 /* AR2315 WMAC (AP51-Full) */ -#define AR5212_AR2317_REV1 0x0091 /* AR2317 WMAC (AP61) */ +#define AR5212_AR2317_REV1 0x0090 /* AR2317 WMAC (AP61-Light) */ +#define AR5212_AR2317_REV2 0x0091 /* AR2317 WMAC (AP61-Full) */ /* AR5212 compatible devid's also attach to 5212 */ #define AR5212_DEVID_0014 0x0014 @@ -82,6 +83,7 @@ #define AR5212_AR2413 0x001a /* AR2413 aka Griffin-lite */ #define AR5212_AR5413 0x001b /* Eagle */ #define AR5212_AR5424 0x001c /* Condor (PCI express) */ +#define AR5212_AR2417 0x001d /* Nala, PCI */ #define AR5212_DEVID_FF19 0xff19 /* XXX PCI express */ /* AR5213 */ ==== //depot/projects/vap/sys/contrib/dev/ath/ah_soc.h#3 (text+ko) ==== @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2006 Sam Leffler, Errno Consulting, Atheros + * Copyright (c) 2006-2008 Sam Leffler, Errno Consulting, Atheros * Communications, Inc. All rights reserved. * * Redistribution and use in source and binary forms are permitted @@ -33,7 +33,7 @@ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGES. * - * $Id: //depot/sw/branches/sam_hal/ah_soc.h#3 $ + * $Id: //depot/sw/branches/sam_hal/ah_soc.h#4 $ */ #ifndef _ATH_AH_SOC_H_ #define _ATH_AH_SOC_H_ ==== //depot/projects/vap/sys/contrib/dev/ath/public/alpha-elf.hal.o.uu#3 (text) ==== @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting, Atheros * Communications, Inc. All rights reserved. * * Redistribution and use in source and binary forms are permitted @@ -33,4404 +33,6573 @@ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGES. * - * $Id: //depot/sw/branches/sam_hal/COPYRIGHT#1 $ + * $Id: //depot/sw/branches/sam_hal/COPYRIGHT#2 $ */ -#define ATH_HAL_VERSION "0.9.20.3" +#define ATH_HAL_VERSION "0.10.5.10" begin 644 hal.o -M?T5,1@(!`0````````````$`)I`!`````````````````````````.CP`P`` -M`````````$```````$``#@`+````NR<``+TC$`#P0Z(5"T(``#TD```!($\` -M0/2A'0M"&@`@Y*%]`T(,`"#DH5D#0D4`(.2A70)"!0`@Y*$Y`D(X`"#DH?4` -M0C,`(/1!`.##H74"0CP`(/0^`.##H54*0C,`(/2A70I"!0`@Y**5`T(``#TD -M```!(#<`0/0U`.##H?4*0BH`(/0R`.##^>XP("$`(.0-`"#\HC420@``/20` -M``$@+`!`]*$]$D($`"#D>O\P(*$W($`F`"#D'P#@P^SO,"`@`"#D(@#@P^WN -M,"`=`"#D`P`@_.[N,"`1`"#D'`#@PP$`/R03\"$@H04!0@``720```(@%P`@ -M]`$`/R0;\2$@H04!0@``720```(@$0`@]`\`X,,``#TD```!(`&`^FL``#TD -M```!(`&`^FL``#TD```!(`&`^FL``#TD```!(`&`^FL``#TD```!(`&`^FL` -M!/]'`8#Z:P``NR<``+TC\/_>(P``7K>,%E\@H@4"0@$`/R0GIR$@H04!0@($ -M040#`$#T2>\P(``$_T<"`"#T$`3Q1YO_7],``%ZG$`#>(P&`^FL``+LG``"] -M(_#_WB,``%ZW`@#P0_G](B`S`"#D#``@_*%=0D`%`"#DH3E"0"D`(.2A]4!` -M+``@]#``X,.A=4)`'P`@].;_(B"A5R!`&@#@P^WN(B`:`"#D"0`@_/GN(B`A -M`"#D`P`@_.SO(B`3`"#D(@#@P^[N(B`6`"#D'P#@PP$`?R0;\6,@H05#0!$` -M(/2A#4-`!0`@Y`$`/R03\"$@H05!0`8`(/04`.##`0`_)!G_(2"A!4%`$``@ -MY!,`'R(``'VG`$!;:P``NB<``+TC#0#@PP``?:<`0%MK``"Z)P``O2,(`.## -M``!]IP!`6VL``+HG``"](P,`X,,`!/]'`0`_(```-+`(``#D>`,@H`@`(+!\ -M`R"@+``@L(`#(*`P`""PA`,@H#0`(+```%ZG$`#>(P&`^FN(`S"R`0`?(`&` -M^FL``+LG``"](]#_WB,``%ZW"``^M1``7K48`'ZU(`">M2@`OK4-!/!'#`3Q -M1PL$\D<)!/]'*O9A2A`$[4<1!.Q'``!]IP!`6VL``+HG``"](P``"T0@]@%( -MH`4*0`$`/R`)``#T"@`?(@``?:<`0%MK``"Z)P``O2,),"!!&?PI(.W_/^P! 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