From owner-p4-projects@FreeBSD.ORG Wed Mar 5 18:05:29 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id DD9D31065676; Wed, 5 Mar 2008 18:05:28 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 9BB95106566C for ; Wed, 5 Mar 2008 18:05:28 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 893408FC1A for ; Wed, 5 Mar 2008 18:05:28 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id m25I5SQG081429 for ; Wed, 5 Mar 2008 18:05:28 GMT (envelope-from rrs@cisco.com) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id m25I5SNk081427 for perforce@freebsd.org; Wed, 5 Mar 2008 18:05:28 GMT (envelope-from rrs@cisco.com) Date: Wed, 5 Mar 2008 18:05:28 GMT Message-Id: <200803051805.m25I5SNk081427@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to rrs@cisco.com using -f From: "Randall R. Stewart" To: Perforce Change Reviews Cc: Subject: PERFORCE change 136929 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 Mar 2008 18:05:29 -0000 http://perforce.freebsd.org/chv.cgi?CH=136929 Change 136929 by rrs@rrs-mips2-jnpr on 2008/03/05 18:05:19 Fix bug in timing setup. They had the structures in the wrong place, resulting in an interrupt every 255*15 instructions. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/dev/rgmii/octeon_rgmx.c#7 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/dev/rgmii/octeon_rgmx.c#7 (text+ko) ==== @@ -1458,10 +1458,10 @@ uint64_t word64; struct { uint64_t rsvd3:4; - uint64_t thr_freq:28; + uint64_t thr_period:28; /* R / O */ uint64_t rsvd2:4; - uint64_t thr_period:20; + uint64_t thr_freq:20; uint64_t rsvd:8; } bits; } octeon_rgmx_pow_int_pc_t;