From owner-svn-src-all@FreeBSD.ORG Tue Mar 24 18:10:23 2009 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 66C5F1065710; Tue, 24 Mar 2009 18:10:23 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 37D0E8FC17; Tue, 24 Mar 2009 18:10:23 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n2OIAMOc053164; Tue, 24 Mar 2009 18:10:22 GMT (envelope-from jhb@svn.freebsd.org) Received: (from jhb@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n2OIAM9t053162; Tue, 24 Mar 2009 18:10:22 GMT (envelope-from jhb@svn.freebsd.org) Message-Id: <200903241810.n2OIAM9t053162@svn.freebsd.org> From: John Baldwin Date: Tue, 24 Mar 2009 18:10:22 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r190386 - in head/sys: amd64/pci i386/pci X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Mar 2009 18:10:27 -0000 Author: jhb Date: Tue Mar 24 18:10:22 2009 New Revision: 190386 URL: http://svn.freebsd.org/changeset/base/190386 Log: Fall back to using configuration type 1 accesses for PCI config requests if the requested PCI bus falls outside of the bus range given in the ACPI MCFG table. Several BIOSes seem to not include all of the PCI busses in systems in their MCFG tables. It maybe that the BIOS is simply buggy and does support all the busses, but it is more conservative to just fall back to the old method unless it is certain that memory accesses will work. Modified: head/sys/amd64/pci/pci_cfgreg.c head/sys/i386/pci/pci_cfgreg.c Modified: head/sys/amd64/pci/pci_cfgreg.c ============================================================================== --- head/sys/amd64/pci/pci_cfgreg.c Tue Mar 24 18:02:35 2009 (r190385) +++ head/sys/amd64/pci/pci_cfgreg.c Tue Mar 24 18:10:22 2009 (r190386) @@ -119,6 +119,7 @@ pci_docfgregread(int bus, int slot, int { if (cfgmech == CFGMECH_PCIE && + (bus >= pcie_minbus && bus <= pcie_maxbus) && (bus != 0 || !(1 << slot & pcie_badslots))) return (pciereg_cfgread(bus, slot, func, reg, bytes)); else @@ -158,6 +159,7 @@ pci_cfgregwrite(int bus, int slot, int f { if (cfgmech == CFGMECH_PCIE && + (bus >= pcie_minbus && bus <= pcie_maxbus) && (bus != 0 || !(1 << slot & pcie_badslots))) pciereg_cfgwrite(bus, slot, func, reg, data, bytes); else Modified: head/sys/i386/pci/pci_cfgreg.c ============================================================================== --- head/sys/i386/pci/pci_cfgreg.c Tue Mar 24 18:02:35 2009 (r190385) +++ head/sys/i386/pci/pci_cfgreg.c Tue Mar 24 18:10:22 2009 (r190386) @@ -206,6 +206,7 @@ pci_docfgregread(int bus, int slot, int { if (cfgmech == CFGMECH_PCIE && + (bus >= pcie_minbus && bus <= pcie_maxbus) && (bus != 0 || !(1 << slot & pcie_badslots))) return (pciereg_cfgread(bus, slot, func, reg, bytes)); else @@ -240,6 +241,7 @@ pci_cfgregwrite(int bus, int slot, int f { if (cfgmech == CFGMECH_PCIE && + (bus >= pcie_minbus && bus <= pcie_maxbus) && (bus != 0 || !(1 << slot & pcie_badslots))) pciereg_cfgwrite(bus, slot, func, reg, data, bytes); else