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From: terry@cs.weber.edu (Terry Lambert)
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Subject: Re: Pouls info request on cache issue
To: bde@zeta.org.au (Bruce Evans)
Date: Thu, 8 Jun 95 15:34:34 MDT
Cc: davidg@FreeBSD.ORG, hackers@FreeBSD.ORG, jkh@FreeBSD.ORG, phk@ref.tfs.com,
        uhclem%nemesis@fw.ast.com
In-Reply-To: <199506081304.XAA25597@godzilla.zeta.org.au> from "Bruce Evans" at Jun 8, 95 11:04:53 pm
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> >Umm, you guys don't use INT 10 to display those messages do you?
> >INT 10 tinkers with a lot of things, including A20 line.
> 
> Does INT 10 really tinker with a lot of things if you just write
> a character [and attribute]?

INT 10 tinkering is implementation defined.

The worst tinkering I've ever seen is ATI and Paradise boards
disabling all other interrupts to do their draws to avoid "sparklies".

These were DRAM boards, so they would otherwise have had to wait
for vertical retrace, giving them lower "winstone" scores.

Yes, that includes serial and ethernet interrupts.

I've actually never seen A20 manipulation in the INT 10 BIOS
routines, but then again I've never run *every* possible card, and
the INT 10 BIOS is hooked to card-supplied ROM during the POST
routine processing for that card, so there *could* be a card that
did what has been claimed.


					Terry Lambert
					terry@cs.weber.edu
---
Any opinions in this posting are my own and not those of my present
or previous employers.