From owner-svn-src-head@FreeBSD.ORG Wed Mar 4 03:51:55 2015 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id B5A99B98; Wed, 4 Mar 2015 03:51:55 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id A13F2C22; Wed, 4 Mar 2015 03:51:55 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t243ptBa091545; Wed, 4 Mar 2015 03:51:55 GMT (envelope-from adrian@FreeBSD.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t243ptau091544; Wed, 4 Mar 2015 03:51:55 GMT (envelope-from adrian@FreeBSD.org) Message-Id: <201503040351.t243ptau091544@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: adrian set sender to adrian@FreeBSD.org using -f From: Adrian Chadd Date: Wed, 4 Mar 2015 03:51:55 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r279578 - head/sys/mips/atheros X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Mar 2015 03:51:55 -0000 Author: adrian Date: Wed Mar 4 03:51:54 2015 New Revision: 279578 URL: https://svnweb.freebsd.org/changeset/base/279578 Log: Add DDR flush registers for QCA955x. Modified: head/sys/mips/atheros/qca955xreg.h Modified: head/sys/mips/atheros/qca955xreg.h ============================================================================== --- head/sys/mips/atheros/qca955xreg.h Wed Mar 4 03:48:11 2015 (r279577) +++ head/sys/mips/atheros/qca955xreg.h Wed Mar 4 03:51:54 2015 (r279578) @@ -198,4 +198,11 @@ #define QCA955X_PLL_VAL_100 0x00000101 #define QCA955X_PLL_VAL_10 0x00001616 +/* DDR block */ +#define QCA955X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x9c) +#define QCA955X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0xa0) +#define QCA955X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4) +#define QCA955X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8) +#define QCA955X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac) + #endif /* __QCA955XREG_H__ */