Date: Fri, 26 Mar 2004 17:30:55 -0500 From: William Kirkland <wek48@.FreeBSD.ORG> To: freebsd-multimedia@freebsd.org Subject: bktr0: Pinnacle PCTV Rave, MT2032 tuner. Message-ID: <20040326223055.GA22580@openwire>
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Hi,
I have installed a Pinnacle, PCTV Rave ... but am unable to change
the channel. After applying the patch, I was able to detect the tuner,
but then had no signal, either audio or video. I did use the `setenv
hw.bt848.tuner=x`, cycling through the 13 different tuners, with no
success (both pre and post patch).
Does anyone know who might be working on this? or where I might obtain
some doucmentation as to how to build/modify a driver?
If I missed some configuration issue, PLEASE let me know that too.
wek@ash: $ fxtv -debug startup
Fxtv v1.03
DETECTED CAPTURE CARD(S) [DRIVER PROBES]:
bktr_mem: memory holder loaded
Pentium Pro MTRR support enabled
bktr0: <BrookTree 878> mem 0xdc100000-0xdc100fff irq 10 at device 0.0 on pci1
bktr0: Warning - card vendor 0x11bd (model 0x0012) unknown.
bktr0: Pinnacle/Miro TV, <no> tuner.
pci1: <multimedia> at device 0.1 (no driver attached)
SYSCTL MIB VALUES:
kern.version: FreeBSD 5.2.1-RC #0: Tue Mar 23 06:18:56 GMT 2004
root@ash.wek4.com:/usr/obj/usr/src/sys/wek-040323
hw.bt848.card: 1
hw.bt848.tuner: -1
hw.bt848.reverse_mute: -1
hw.bt848.format: -1
hw.bt848.slow_msp_audio: -1
TUNER SIGNATURE (0x01 - 0xff):
00 00 00 00 00 00 00 00 08 00 01 00 00 00 00 00
TUNER I2C DEVICES FOUND AT:
0x86, 0xa0
CAPTURE CARD EEPROM CONTENTS:
Read 256 EEPROM bytes (0x00 - 0xff)
f0 00 00 00 3b ff ff ff ff ff ff ff ff ff ff ff
f0 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
45 6d 70 54 79 56 ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
30 30 30 33 ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
30 30 30 30 ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
32 30 33 35 36 30 36 36 39 35 33 34 34 32 31 38
34 32 ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff 00 12 11 bd
SUPPORTED FREQUENCY SETS:
1 nabcst
2 cableirc
3 cablehrc
4 weurope
5 jpnbcst
6 jpncable
7 xussr
8 australia
9 france
Supported RGB Capture Pixel Formats:
bpp Bpp RGB Masks Swap
--- --- ---------------------------- ----
15 2 00007c00, 000003e0, 0000001f NB
16 2 0000f800, 000007e0, 0000001f NB
24 3 00ff0000, 0000ff00, 000000ff B
24 4 00ff0000, 0000ff00, 000000ff NBWb
Supported YUV Capture Pixel Formats:
YUVSize HSamp VSamp Pack CompOrder T->B L->R YTrans
------- ----- ----- ------ --------- ---- ---- ------
8,8,8 1,2,2 1,1,1 PLANAR YUV Y Y N
8,8,8 1,2,2 1,1,1 PACKED YUYV Y Y N
8,8,8 1,2,2 1,2,2 PLANAR YUV Y Y N
XSERVER: 'The XFree86 Project, Inc' v40300000, Protocol Verson 11.0
Screen Res = 1024x768, DefDepth = 24; NumScreens = 1
Bitmap Unit/BitOrder/Pad = 32/LSBFirst/32, Image ByteOrder = LSBFirst
Xlib: extension "XFree86-DGA" missing on display ":0.0".
XF86DGA{QueryVersion,QueryDirectVideo}() failed
Rating Available Visuals:
Rating Class bpp Bpp R,G,B Masks Swap DirectVid
------ ----------- --- --- ---------------------------- ---- ---------
4 TrueColor 24 4,4 00ff0000, 0000ff00, 000000ff -- No
Chosen Visual is 24-bpp TrueColor
XF86VidModeQueryVersion() succeeded - version = 2.02
wek@ash: $ fxtv -debug startup
Fxtv v1.03
DETECTED CAPTURE CARD(S) [DRIVER PROBES]:
bktr_mem: memory holder loaded
Pentium Pro MTRR support enabled
bktr0: <BrookTree 878> mem 0xdc100000-0xdc100fff irq 10 at device 0.0 on pci1
bktr0: tuner @ 0xc0
bktr0: MT2032: Companycode=3cbf Part=00 Revision=00
bktr0: Pinnacle PCTV Rave, MT2032 tuner.
SYSCTL MIB VALUES:
kern.version: FreeBSD 5.2.1-RC #0: Thu Mar 25 00:03:42 PST 2004
root@ash.wek4.com:/usr/obj/usr/src/sys/wek-040325
hw.bt848.card: 1
hw.bt848.tuner: 13
hw.bt848.reverse_mute: -1
hw.bt848.format: -1
hw.bt848.slow_msp_audio: -1
TUNER SIGNATURE (0x01 - 0xff):
00 00 00 00 00 00 00 00 08 00 01 00 00 00 00 00
TUNER I2C DEVICES FOUND AT:
0x86, 0xa0
CAPTURE CARD EEPROM CONTENTS:
Read 256 EEPROM bytes (0x00 - 0xff)
f0 00 00 00 3b ff ff ff ff ff ff ff ff ff ff ff
f0 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
45 6d 70 54 79 56 ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
30 30 30 33 ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
30 30 30 30 ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
32 30 33 35 36 30 36 36 39 35 33 34 34 32 31 38
34 32 ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff 00 12 11 bd
SUPPORTED FREQUENCY SETS:
1 nabcst
2 cableirc
3 cablehrc
4 weurope
5 jpnbcst
6 jpncable
7 xussr
8 australia
9 france
Supported RGB Capture Pixel Formats:
bpp Bpp RGB Masks Swap
--- --- ---------------------------- ----
15 2 00007c00, 000003e0, 0000001f NB
16 2 0000f800, 000007e0, 0000001f NB
24 3 00ff0000, 0000ff00, 000000ff B
24 4 00ff0000, 0000ff00, 000000ff NBWb
Supported YUV Capture Pixel Formats:
YUVSize HSamp VSamp Pack CompOrder T->B L->R YTrans
------- ----- ----- ------ --------- ---- ---- ------
8,8,8 1,2,2 1,1,1 PLANAR YUV Y Y N
8,8,8 1,2,2 1,1,1 PACKED YUYV Y Y N
8,8,8 1,2,2 1,2,2 PLANAR YUV Y Y N
XSERVER: 'The XFree86 Project, Inc' v40300000, Protocol Verson 11.0
Screen Res = 1024x768, DefDepth = 24; NumScreens = 1
Bitmap Unit/BitOrder/Pad = 32/LSBFirst/32, Image ByteOrder = LSBFirst
XF86DGA{QueryVersion,QueryDirectVideo}() failed
Rating Available Visuals:
Rating Class bpp Bpp R,G,B Masks Swap DirectVid
------ ----------- --- --- ---------------------------- ---- ---------
4 TrueColor 24 4,4 00ff0000, 0000ff00, 000000ff -- No
Chosen Visual is 24-bpp TrueColor
XF86VidModeQueryVersion() succeeded - version = 2.02
wek@ash: $ ls -l bktr-pctv-rave.diff
-rw-r--r-- 1 wek wheel 13764 Mar 24 23:54 bktr-pctv-rave.diff
wek@ash: $ md5 bktr-pctv-rave.diff
MD5 (bktr-pctv-rave.diff) = 382f98eb137af9728fe53646f12e8063
wek@ash: $ cat bktr-pctv-rave.diff
diff -c .org/bktr_card.c ./bktr_card.c
*** .org/bktr_card.c Sat Feb 8 03:04:57 2003
--- ./bktr_card.c Fri Nov 7 00:30:20 2003
***************
*** 355,360 ****
--- 355,372 ----
{ 0x10000, 0, 0x10000, 0, 1 }, /* audio MUX values */
0x10f00 }, /* GPIO mask */
+ { CARD_PINNACLE_PCTV_RAVE, /* the card id */
+ "Pinnacle PCTV Rave", /* the 'name' */
+ NULL, /* the tuner */
+ 0, /* the tuner i2c address */
+ 0, /* dbx unknown */
+ 0,
+ 0,
+ 0, /* EEProm unknown */
+ 0, /* size unknown */
+ { 0x02, 0x01, 0x00, 0x0a, 1 }, /* audio MUX values */
+ 0x03000F }, /* GPIO mask */
+
};
struct bt848_card_sig bt848_card_signature[1]= {
***************
*** 554,559 ****
--- 566,572 ----
#define PCI_VENDOR_FLYVIDEO_2 0x1852
#define PCI_VENDOR_PINNACLE_ALT 0xBD11
#define PCI_VENDOR_IODATA 0x10fc
+ #define PCI_VENDOR_PINNACLE_NEW 0x11BD
#define MODEL_IODATA_GV_BCTV3_PCI 0x4020
***************
*** 696,701 ****
--- 709,729 ----
bktr->card.eepromSize = (u_char)(256 / EEPROMBLOCKSIZE);
goto checkTuner;
}
+
+ if (subsystem_vendor_id == PCI_VENDOR_PINNACLE_NEW) {
+ bktr->card = cards[ (card = CARD_PINNACLE_PCTV_RAVE) ];
+ bktr->card.eepromAddr = eeprom_i2c_address;
+ bktr->card.eepromSize = (u_char)(256 / EEPROMBLOCKSIZE);
+
+ TDA9887_init(bktr, 0);
+
+ /* look for a tuner */
+ tuner_i2c_address = locate_tuner_address( bktr );
+ printf( "%s: tuner @ %#x\n", bktr_name(bktr), tuner_i2c_address );
+ select_tuner( bktr, TUNER_MT2032 );
+
+ goto checkDBX;
+ }
/* Vendor is unknown. We will use the standard probe code */
/* which may not give best results */
diff -c .org/bktr_card.h ./bktr_card.h
*** .org/bktr_card.h Sat Feb 8 03:04:57 2003
--- ./bktr_card.h Thu Aug 28 23:36:45 2003
***************
*** 77,83 ****
#define CARD_LEADTEK 15
#define CARD_TERRATVPLUS 16
#define CARD_IO_BCTV3 17
! #define Bt848_MAX_CARD 18
#define CARD_IO_GV CARD_IO_BCTV2
--- 77,84 ----
#define CARD_LEADTEK 15
#define CARD_TERRATVPLUS 16
#define CARD_IO_BCTV3 17
! #define CARD_PINNACLE_PCTV_RAVE 18
! #define Bt848_MAX_CARD 19
#define CARD_IO_GV CARD_IO_BCTV2
diff -c .org/bktr_tuner.c ./bktr_tuner.c
*** .org/bktr_tuner.c Thu Oct 26 18:38:46 2000
--- ./bktr_tuner.c Fri Aug 29 00:16:29 2003
***************
*** 137,142 ****
--- 137,146 ----
#define TSBH1_FCONTROL 0xce
+ static void mt2032_set_tv_freq(bktr_ptr_t bktr, unsigned int freq);
+ static int mt2032_init(bktr_ptr_t bktr);
+
+
static const struct TUNER tuners[] = {
/* XXX FIXME: fill in the band-switch crosspoints */
/* NO_TUNER */
***************
*** 277,283 ****
TSBH1_FCONTROL,
0x00 },
{ 0x00, 0x00 }, /* band-switch crosspoints */
! { 0x01, 0x02, 0x08, 0x00 } } /* the band-switch values */
};
--- 281,297 ----
TSBH1_FCONTROL,
0x00 },
{ 0x00, 0x00 }, /* band-switch crosspoints */
! { 0x01, 0x02, 0x08, 0x00 } }, /* the band-switch values */
!
! /* MT2032 Microtune */
! { "MT2032", /* the 'name' */
! TTYPE_PAL, /* input type */
! { TSA552x_SCONTROL, /* control byte for Tuner PLL */
! TSA552x_SCONTROL,
! TSA552x_SCONTROL,
! 0x00 },
! { 0x00, 0x00 }, /* band-switch crosspoints */
! { 0xa0, 0x90, 0x30, 0x00 } }, /* the band-switch values */
};
***************
*** 711,716 ****
--- 725,733 ----
} else {
bktr->card.tuner = NULL;
}
+ if (tuner_type == TUNER_MT2032) {
+ mt2032_init(bktr);
+ }
}
/*
***************
*** 788,793 ****
--- 805,814 ----
if ( tuner == NULL )
return( -1 );
+ if (tuner == &tuners[TUNER_MT2032]) {
+ mt2032_set_tv_freq(bktr, frequency);
+ return 0;
+ }
if (type == TV_FREQUENCY) {
/*
* select the band based on frequency
***************
*** 975,980 ****
--- 996,1003 ----
* Get the Tuner status and signal strength
*/
int get_tuner_status( bktr_ptr_t bktr ) {
+ if (bktr->card.tuner == &tuners[TUNER_MT2032])
+ return 0;
return i2cRead( bktr, bktr->card.tuner_pllAddr + 1 );
}
***************
*** 1013,1016 ****
--- 1036,1409 ----
chnlset->max_channel=freqTable[chnlset->index].ptr[0];
return( 0 );
+ }
+
+
+
+
+ #define TDA9887_ADDR 0x86
+
+ int
+ TDA9887_init(bktr_ptr_t bktr, int output2_enable)
+ {
+ u_char addr = TDA9887_ADDR;
+ #if 0
+ char buf[8];
+
+ /* NOTE: these are PAL values */
+ buf[0] = 0; /* sub address */
+ buf[1] = 0x50; /* output port1 inactive */
+ buf[2] = 0x6e; /* tuner takeover point / de-emphasis */
+ buf[3] = 0x09; /* fVIF = 38.9 MHz, fFM = 5.5 MHz */
+
+ if (!output2_enable)
+ buf[1] |= 0x80;
+
+ if (i2cWriteBuf(bktr, addr, 4, buf) == -1) {
+ printf("%s: TDA9887 write failed\n", bktr_name(bktr));
+ return -1;
+ }
+ #else
+ i2cWrite(bktr, addr, 0, output2_enable ? 0x50 : 0xd0);
+ i2cWrite(bktr, addr, 1, 0x6e);
+ i2cWrite(bktr, addr, 2, 0x09);
+ #endif
+ return 0;
+ }
+
+
+
+ #define MT2032_OPTIMIZE_VCO 1
+
+ /* holds the value of XOGC register after init */
+ static int MT2032_XOGC = 4;
+
+ /* card.tuner_pllAddr not set during init */
+ #define MT2032_ADDR 0xc0
+
+ #ifndef MT2032_ADDR
+ #define MT2032_ADDR (bktr->card.tuner_pllAddr)
+ #endif
+
+ static u_char
+ _MT2032_GetRegister(bktr_ptr_t bktr, u_char regNum)
+ {
+ int ch;
+
+ if (i2cWrite(bktr, MT2032_ADDR, regNum, -1) == -1) {
+ printf("%s: MT2032 write failed (i2c addr %#x)\n",
+ bktr_name(bktr), MT2032_ADDR);
+ }
+ if ((ch = i2cRead(bktr, MT2032_ADDR + 1)) == -1) {
+ printf("%s: MT2032 get register %d failed\n",
+ bktr_name(bktr), regNum);
+ return 0;
+ }
+ return ch;
+ }
+
+ static void
+ _MT2032_SetRegister(bktr_ptr_t bktr, u_char regNum, u_char data)
+ {
+ i2cWrite(bktr, MT2032_ADDR, regNum, data);
+ }
+
+ #define MT2032_GetRegister(r) _MT2032_GetRegister(bktr,r)
+ #define MT2032_SetRegister(r,d) _MT2032_SetRegister(bktr,r,d)
+
+
+ static int
+ mt2032_init(bktr_ptr_t bktr)
+ {
+ u_char rdbuf[22];
+ int xogc, xok = 0;
+ int i;
+
+ TDA9887_init(bktr, 0);
+
+ for (i = 0; i < 21; i++)
+ rdbuf[i] = MT2032_GetRegister(i);
+
+ printf("%s: MT2032: Companycode=%02x%02x Part=%02x Revision=%02x\n",
+ bktr_name(bktr),
+ rdbuf[0x11], rdbuf[0x12], rdbuf[0x13], rdbuf[0x14]);
+
+ /* Initialize Registers per spec. */
+ MT2032_SetRegister(2, 0xff);
+ MT2032_SetRegister(3, 0x0f);
+ MT2032_SetRegister(4, 0x1f);
+ MT2032_SetRegister(6, 0xe4);
+ MT2032_SetRegister(7, 0x8f);
+ MT2032_SetRegister(8, 0xc3);
+ MT2032_SetRegister(9, 0x4e);
+ MT2032_SetRegister(10, 0xec);
+ MT2032_SetRegister(13, 0x32);
+
+ /* Adjust XOGC (register 7), wait for XOK */
+ xogc = 7;
+ do {
+ DELAY(10000);
+ xok = MT2032_GetRegister(0x0e) & 0x01;
+ if (xok == 1) {
+ break;
+ }
+ xogc--;
+ if (xogc == 3) {
+ xogc = 4; /* min. 4 per spec */
+ break;
+ }
+ MT2032_SetRegister(7, 0x88 + xogc);
+ } while (xok != 1);
+
+ TDA9887_init(bktr, 1);
+
+ MT2032_XOGC = xogc;
+
+ return 0;
+ }
+
+ static int
+ MT2032_SpurCheck(int f1, int f2, int spectrum_from, int spectrum_to)
+ {
+ int n1 = 1, n2, f;
+
+ f1 = f1 / 1000; /* scale to kHz to avoid 32bit overflows */
+ f2 = f2 / 1000;
+ spectrum_from /= 1000;
+ spectrum_to /= 1000;
+
+ do {
+ n2 = -n1;
+ f = n1 * (f1 - f2);
+ do {
+ n2--;
+ f = f - f2;
+ if ((f > spectrum_from) && (f < spectrum_to)) {
+ return 1;
+ }
+ } while ((f > (f2 - spectrum_to)) || (n2 > -5));
+ n1++;
+ } while (n1 < 5);
+
+ return 0;
+ }
+
+ static int
+ MT2032_ComputeFreq(
+ int rfin,
+ int if1,
+ int if2,
+ int spectrum_from,
+ int spectrum_to,
+ unsigned char *buf,
+ int *ret_sel,
+ int xogc
+ )
+ { /* all in Hz */
+ int fref, lo1, lo1n, lo1a, s, sel;
+ int lo1freq, desired_lo1, desired_lo2, lo2, lo2n, lo2a,
+ lo2num, lo2freq;
+ int nLO1adjust;
+
+ fref = 5250 * 1000; /* 5.25MHz */
+
+ /* per spec 2.3.1 */
+ desired_lo1 = rfin + if1;
+ lo1 = (2 * (desired_lo1 / 1000) + (fref / 1000)) / (2 * fref / 1000);
+ lo1freq = lo1 * fref;
+ desired_lo2 = lo1freq - rfin - if2;
+
+ /* per spec 2.3.2 */
+ for (nLO1adjust = 1; nLO1adjust < 3; nLO1adjust++) {
+ if (!MT2032_SpurCheck(lo1freq, desired_lo2, spectrum_from, spectrum_to)) {
+ break;
+ }
+ if (lo1freq < desired_lo1) {
+ lo1 += nLO1adjust;
+ } else {
+ lo1 -= nLO1adjust;
+ }
+
+ lo1freq = lo1 * fref;
+ desired_lo2 = lo1freq - rfin - if2;
+ }
+
+ /* per spec 2.3.3 */
+ s = lo1freq / 1000 / 1000;
+
+ if (MT2032_OPTIMIZE_VCO) {
+ if (s > 1890) {
+ sel = 0;
+ } else if (s > 1720) {
+ sel = 1;
+ } else if (s > 1530) {
+ sel = 2;
+ } else if (s > 1370) {
+ sel = 3;
+ } else {
+ sel = 4;/* >1090 */
+ }
+ } else {
+ if (s > 1790) {
+ sel = 0;/* <1958 */
+ } else if (s > 1617) {
+ sel = 1;
+ } else if (s > 1449) {
+ sel = 2;
+ } else if (s > 1291) {
+ sel = 3;
+ } else {
+ sel = 4;/* >1090 */
+ }
+ }
+
+ *ret_sel = sel;
+
+ /* per spec 2.3.4 */
+ lo1n = lo1 / 8;
+ lo1a = lo1 - (lo1n * 8);
+ lo2 = desired_lo2 / fref;
+ lo2n = lo2 / 8;
+ lo2a = lo2 - (lo2n * 8);
+ /* scale to fit in 32bit arith */
+ lo2num = ((desired_lo2 / 1000) % (fref / 1000)) * 3780 / (fref / 1000);
+ lo2freq = (lo2a + 8 * lo2n) * fref + lo2num * (fref / 1000) / 3780 * 1000;
+
+ if (lo1a < 0 || lo1a > 7 || lo1n < 17 || lo1n > 48 || lo2a < 0 ||
+ lo2a > 7 || lo2n < 17 || lo2n > 30) {
+ printf("MT2032: parameter out of range\n");
+ return -1;
+ }
+ /* set up MT2032 register map for transfer over i2c */
+ buf[0] = lo1n - 1;
+ buf[1] = lo1a | (sel << 4);
+ buf[2] = 0x86; /* LOGC */
+ buf[3] = 0x0f; /* reserved */
+ buf[4] = 0x1f;
+ buf[5] = (lo2n - 1) | (lo2a << 5);
+ if (rfin < 400 * 1000 * 1000) {
+ buf[6] = 0xe4;
+ } else {
+ buf[6] = 0xf4; /* set PKEN per rev 1.2 */
+ }
+
+ buf[7] = 8 + xogc;
+ buf[8] = 0xc3; /* reserved */
+ buf[9] = 0x4e; /* reserved */
+ buf[10] = 0xec; /* reserved */
+ buf[11] = (lo2num & 0xff);
+ buf[12] = (lo2num >> 8) | 0x80; /* Lo2RST */
+
+ return 0;
+ }
+
+ static int
+ MT2032_CheckLOLock(bktr_ptr_t bktr)
+ {
+ int t, lock = 0;
+ for (t = 0; t < 10; t++) {
+ lock = MT2032_GetRegister(0x0e) & 0x06;
+ if (lock == 6) {
+ break;
+ }
+ DELAY(1000);
+ }
+ return lock;
+ }
+
+ static int
+ MT2032_OptimizeVCO(bktr_ptr_t bktr, int sel, int lock)
+ {
+ int tad1, lo1a;
+
+ tad1 = MT2032_GetRegister(0x0f) & 0x07;
+
+ if (tad1 == 0) {
+ return lock;
+ }
+ if (tad1 == 1) {
+ return lock;
+ }
+ if (tad1 == 2) {
+ if (sel == 0) {
+ return lock;
+ } else {
+ sel--;
+ }
+ } else {
+ if (sel < 4) {
+ sel++;
+ } else {
+ return lock;
+ }
+ }
+ lo1a = MT2032_GetRegister(0x01) & 0x07;
+ MT2032_SetRegister(0x01, lo1a | (sel << 4));
+ lock = MT2032_CheckLOLock(bktr);
+ return lock;
+ }
+
+ static int
+ MT2032_SetIFFreq(bktr_ptr_t bktr, int rfin, int if1, int if2, int from, int to)
+ {
+ u_char buf[21];
+ int lint_try, sel, lock = 0;
+
+ if (MT2032_ComputeFreq(rfin, if1, if2, from, to, &buf[0], &sel, MT2032_XOGC) == -1)
+ return -1;
+
+ TDA9887_init(bktr, 0);
+
+ printf("%s: MT2032-SetIFFreq: 0x%02X%02X%02X%02X...\n",
+ bktr_name(bktr),
+ buf[0x00], buf[0x01], buf[0x02], buf[0x03]);
+
+ /* send only the relevant registers per Rev. 1.2 */
+ MT2032_SetRegister(0, buf[0x00]);
+ MT2032_SetRegister(1, buf[0x01]);
+ MT2032_SetRegister(2, buf[0x02]);
+
+ MT2032_SetRegister(5, buf[0x05]);
+ MT2032_SetRegister(6, buf[0x06]);
+ MT2032_SetRegister(7, buf[0x07]);
+
+ MT2032_SetRegister(11, buf[0x0B]);
+ MT2032_SetRegister(12, buf[0x0C]);
+
+ /* wait for PLLs to lock (per manual), retry LINT if not. */
+ for (lint_try = 0; lint_try < 2; lint_try++) {
+ lock = MT2032_CheckLOLock(bktr);
+
+ if (MT2032_OPTIMIZE_VCO) {
+ lock = MT2032_OptimizeVCO(bktr, sel, lock);
+ }
+ if (lock == 6) {
+ break;
+ }
+ /* set LINT to re-init PLLs */
+ MT2032_SetRegister(7, 0x80 + 8 + MT2032_XOGC);
+ DELAY(10000);
+ MT2032_SetRegister(7, 8 + MT2032_XOGC);
+ }
+ if (lock != 6)
+ printf("%s: PLL didn't lock\n", bktr_name(bktr));
+
+ MT2032_SetRegister(2, 0x20);
+
+ TDA9887_init(bktr, 1);
+ return 0;
+ }
+
+ static void
+ mt2032_set_tv_freq(bktr_ptr_t bktr, unsigned int freq)
+ {
+ int if2,from,to;
+
+ from=32900*1000;
+ to=39900*1000;
+ if2=38900*1000;
+
+ printf("%s: setting frequency to %d\n", bktr_name(bktr), freq*62500);
+ MT2032_SetIFFreq(bktr, freq*62500 /* freq*1000*1000/16 */,
+ 1090*1000*1000, if2, from, to);
}
diff -c .org/bktr_tuner.h ./bktr_tuner.h
*** .org/bktr_tuner.h Mon Sep 27 00:06:20 1999
--- ./bktr_tuner.h Thu Aug 28 23:34:20 2003
***************
*** 59,65 ****
#define PHILIPS_FR1236_SECAM 11 /* These have FM radio support */
#define ALPS_TSCH5 12
#define ALPS_TSBH1 13
! #define Bt848_MAX_TUNER 14
/* experimental code for Automatic Frequency Control */
#define TUNER_AFC
--- 59,66 ----
#define PHILIPS_FR1236_SECAM 11 /* These have FM radio support */
#define ALPS_TSCH5 12
#define ALPS_TSBH1 13
! #define TUNER_MT2032 14
! #define Bt848_MAX_TUNER 15
/* experimental code for Automatic Frequency Control */
#define TUNER_AFC
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