Date: Fri, 30 Jul 1999 10:40:34 -0700 (PDT) From: "Eric J. Schwertfeger" <ejs@bfd.com> To: "freebsd-smp@FreeBSD.ORG" <freebsd-smp@FreeBSD.ORG> Subject: SMP and the Celeron Message-ID: <Pine.BSF.4.05.9907301022080.12170-100000@harlie.bfd.com>
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(All of this is just my opinion, feel free to disagree or kibitz. With the recent threads, I thought that this needs to be said so that readers can make informed decisions). After having played with a dual Celeron system, and owning a dual PPro w/512K cache per CPU, it would seem that the Celeron box benefits less from SMP than the PPro box does. The make world time on the PPro box is much less under SMP, but for the Celeron box, it's only 20% faster. (BTW, how is 49min37sec for a 3.2R make world on a single-HD system?) Still, a single Celeron does a make world faster than the dual PPro box (possibly due to lame IDE HD in dual PPro box). After having played around with it, it seems to come down to memory bandwidth. Since the Celerons have a quarter the L2 cache of the PPros I've got, they are probably more dependant on memory bandwidth for performance, and SMP just adds to the problem with bus contention. Processes that tend to fit in the L2 Celeron cache, such as gzip, do approach an 80-90% improvement with SMP, but overall, I'm seeing more of a 40-50% improvement. Between this and the rumors that Intel is going to disable Celeron SMP in the next Celeron revision, I have to consider Celeron SMP an interesting experiment, but not something you'd actually use in a production environment. It's a good way to experiment with SMP for SMP's sake, but unless you're doing the kind of stuff that does fit in the L2 cache, the performance gain isn't what you'd hope for. To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-smp" in the body of the message
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