Date: Wed, 11 May 2016 06:27:47 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r299409 - head/sys/dev/siba Message-ID: <201605110627.u4B6RlG2041810@repo.freebsd.org>
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Author: adrian Date: Wed May 11 06:27:46 2016 New Revision: 299409 URL: https://svnweb.freebsd.org/changeset/base/299409 Log: [siba] add r4 and r8 sprom formats for core_pwr_info. The upcoming bwn(4) N-PHY support requires this (among other things that are (hopefully) upcoming.) Obtained from: Linux ssb (definitions) Modified: head/sys/dev/siba/siba_bwn.c head/sys/dev/siba/siba_core.c head/sys/dev/siba/sibareg.h head/sys/dev/siba/sibavar.h Modified: head/sys/dev/siba/siba_bwn.c ============================================================================== --- head/sys/dev/siba/siba_bwn.c Wed May 11 06:27:00 2016 (r299408) +++ head/sys/dev/siba/siba_bwn.c Wed May 11 06:27:46 2016 (r299409) @@ -93,7 +93,7 @@ static const struct siba_dev { { PCI_VENDOR_BROADCOM, 0x4324, "Broadcom BCM4309 802.11a/b/g Wireless" }, { PCI_VENDOR_BROADCOM, 0x4325, "Broadcom BCM4306 802.11b/g Wireless" }, - { PCI_VENDOR_BROADCOM, 0x4328, "Unknown" }, + { PCI_VENDOR_BROADCOM, 0x4328, "Broadcom BCM4321 802.11a/b/g Wireless" }, { PCI_VENDOR_BROADCOM, 0x4329, "Unknown" }, { PCI_VENDOR_BROADCOM, 0x432b, "Unknown" } }; Modified: head/sys/dev/siba/siba_core.c ============================================================================== --- head/sys/dev/siba/siba_core.c Wed May 11 06:27:00 2016 (r299408) +++ head/sys/dev/siba/siba_core.c Wed May 11 06:27:46 2016 (r299409) @@ -1574,6 +1574,10 @@ siba_sprom_r45(struct siba_sprom *out, c int i; uint16_t v; uint16_t mac_80211bg_offset; + const uint16_t pwr_info_offset[] = { + SIBA_SPROM4_PWR_INFO_CORE0, SIBA_SPROM4_PWR_INFO_CORE1, + SIBA_SPROM4_PWR_INFO_CORE2, SIBA_SPROM4_PWR_INFO_CORE3 + }; if (out->rev == 4) mac_80211bg_offset = SIBA_SPROM4_MAC_80211BG; @@ -1618,6 +1622,43 @@ siba_sprom_r45(struct siba_sprom *out, c SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN2); SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN3); bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5)); + + /* Extract core power info */ + for (i = 0; i < nitems(pwr_info_offset); i++) { + uint16_t o = pwr_info_offset[i]; + + SIBA_SHIFTOUT(core_pwr_info[i].itssi_2g, o + SIBA_SPROM4_2G_MAXP_ITSSI, + SIBA_SPROM4_2G_ITSSI); + SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_2g, o + SIBA_SPROM4_2G_MAXP_ITSSI, + SIBA_SPROM4_2G_MAXP); + + SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[0], o + SIBA_SPROM4_2G_PA_0, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[1], o + SIBA_SPROM4_2G_PA_1, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[2], o + SIBA_SPROM4_2G_PA_2, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[3], o + SIBA_SPROM4_2G_PA_3, ~0); + + SIBA_SHIFTOUT(core_pwr_info[i].itssi_5g, o + SIBA_SPROM4_5G_MAXP_ITSSI, + SIBA_SPROM4_5G_ITSSI); + SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5g, o + SIBA_SPROM4_5G_MAXP_ITSSI, + SIBA_SPROM4_5G_MAXP); + SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gh, o + SIBA_SPROM4_5GHL_MAXP, + SIBA_SPROM4_5GH_MAXP); + SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gl, o + SIBA_SPROM4_5GHL_MAXP, + SIBA_SPROM4_5GL_MAXP); + + SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[0], o + SIBA_SPROM4_5GL_PA_0, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[1], o + SIBA_SPROM4_5GL_PA_1, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[2], o + SIBA_SPROM4_5GL_PA_2, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[3], o + SIBA_SPROM4_5GL_PA_3, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[0], o + SIBA_SPROM4_5G_PA_0, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[1], o + SIBA_SPROM4_5G_PA_1, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[2], o + SIBA_SPROM4_5G_PA_2, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[3], o + SIBA_SPROM4_5G_PA_3, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[0], o + SIBA_SPROM4_5GH_PA_0, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[1], o + SIBA_SPROM4_5GH_PA_1, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[2], o + SIBA_SPROM4_5GH_PA_2, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[3], o + SIBA_SPROM4_5GH_PA_3, ~0); + } } static void @@ -1625,6 +1666,10 @@ siba_sprom_r8(struct siba_sprom *out, co { int i; uint16_t v; + uint16_t pwr_info_offset[] = { + SIBA_SROM8_PWR_INFO_CORE0, SIBA_SROM8_PWR_INFO_CORE1, + SIBA_SROM8_PWR_INFO_CORE2, SIBA_SROM8_PWR_INFO_CORE3 + }; for (i = 0; i < 3; i++) { v = in[SIBA_OFFSET(SIBA_SPROM8_MAC_80211BG) + i]; @@ -1712,6 +1757,38 @@ siba_sprom_r8(struct siba_sprom *out, co SSB_SROM8_FEM_TR_ISO); SIBA_SHIFTOUT(fem.ghz5.antswlut, SIBA_SPROM8_FEM5G, SSB_SROM8_FEM_ANTSWLUT); + + /* Extract cores power info info */ + for (i = 0; i < nitems(pwr_info_offset); i++) { + uint16_t o = pwr_info_offset[i]; + SIBA_SHIFTOUT(core_pwr_info[i].itssi_2g, o + SIBA_SROM8_2G_MAXP_ITSSI, + SIBA_SPROM8_2G_ITSSI); + SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_2g, o + SIBA_SROM8_2G_MAXP_ITSSI, + SIBA_SPROM8_2G_MAXP); + + SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[0], o + SIBA_SROM8_2G_PA_0, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[1], o + SIBA_SROM8_2G_PA_1, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[2], o + SIBA_SROM8_2G_PA_2, ~0); + + SIBA_SHIFTOUT(core_pwr_info[i].itssi_5g, o + SIBA_SROM8_5G_MAXP_ITSSI, + SIBA_SPROM8_5G_ITSSI); + SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5g, o + SIBA_SROM8_5G_MAXP_ITSSI, + SIBA_SPROM8_5G_MAXP); + SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gh, o + SIBA_SPROM8_5GHL_MAXP, + SIBA_SPROM8_5GH_MAXP); + SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gl, o + SIBA_SPROM8_5GHL_MAXP, + SIBA_SPROM8_5GL_MAXP); + + SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[0], o + SIBA_SROM8_5GL_PA_0, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[1], o + SIBA_SROM8_5GL_PA_1, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[2], o + SIBA_SROM8_5GL_PA_2, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[0], o + SIBA_SROM8_5G_PA_0, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[1], o + SIBA_SROM8_5G_PA_1, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[2], o + SIBA_SROM8_5G_PA_2, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[0], o + SIBA_SROM8_5GH_PA_0, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[1], o + SIBA_SROM8_5GH_PA_1, ~0); + SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[2], o + SIBA_SROM8_5GH_PA_2, ~0); + } } static int8_t @@ -2628,3 +2705,18 @@ siba_fix_imcfglobug(device_t dev) } siba_write_4_sub(sd, SIBA_IMCFGLO, tmp); } + +int +siba_sprom_get_core_power_info(device_t dev, int core, + struct siba_sprom_core_pwr_info *c) +{ + struct siba_dev_softc *sd = device_get_ivars(dev); + struct siba_softc *siba = sd->sd_bus; + + if (core < 0 || core > 3) { + return (EINVAL); + } + memcpy(c, &siba->siba_sprom.core_pwr_info[core], sizeof(*c)); + return (0); +} + Modified: head/sys/dev/siba/sibareg.h ============================================================================== --- head/sys/dev/siba/sibareg.h Wed May 11 06:27:00 2016 (r299408) +++ head/sys/dev/siba/sibareg.h Wed May 11 06:27:46 2016 (r299409) @@ -289,7 +289,7 @@ #define SIBA_IDHIGH_REVHI_SHIFT 8 #define SIBA_IDHIGH_REV(id) \ ((id & SIBA_IDHIGH_REVLO) | ((id & SIBA_IDHIGH_REVHI) >> \ - SIBA_IDHIGH_REVHI_SHIFT)) + SIBA_IDHIGH_REVHI_SHIFT)) #define SIBA_IDHIGH_VENDORMASK 0xFFFF0000 /* Vendor Code */ #define SIBA_IDHIGH_VENDOR_SHIFT 16 #define SIBA_IDHIGH_VENDOR(id) \ @@ -299,6 +299,7 @@ #define SIBA_SPROMSIZE_R4 220 #define SIBA_SPROM_BASE 0x1000 #define SIBA_SPROM_REV_CRC 0xff00 + #define SIBA_SPROM1_MAC_80211BG 0x1048 #define SIBA_SPROM1_MAC_ETH 0x104e #define SIBA_SPROM1_MAC_80211A 0x1054 @@ -334,8 +335,11 @@ #define SIBA_SPROM1_AGAIN 0x1074 #define SIBA_SPROM1_AGAIN_BG 0x00ff #define SIBA_SPROM1_AGAIN_A 0xff00 + #define SIBA_SPROM2_BFHIGH 0x1038 + #define SIBA_SPROM3_MAC_80211BG 0x104a + #define SIBA_SPROM4_MAC_80211BG 0x104c #define SIBA_SPROM4_ETHPHY 0x105a #define SIBA_SPROM4_ETHPHY_ET0A 0x001f @@ -364,6 +368,42 @@ #define SIBA_SPROM4_GPIOB 0x1058 #define SIBA_SPROM4_GPIOB_P2 0x00ff #define SIBA_SPROM4_GPIOB_P3 0xff00 + +/* The following four blocks share the same structure */ +#define SIBA_SPROM4_PWR_INFO_CORE0 0x0080 +#define SIBA_SPROM4_PWR_INFO_CORE1 0x00AE +#define SIBA_SPROM4_PWR_INFO_CORE2 0x00DC +#define SIBA_SPROM4_PWR_INFO_CORE3 0x010A + +#define SIBA_SPROM4_2G_MAXP_ITSSI 0x00 /* 2 GHz ITSSI and 2 GHz Max Power */ +#define SIBA_SPROM4_2G_MAXP 0x00FF +#define SIBA_SPROM4_2G_ITSSI 0xFF00 +#define SIBA_SPROM4_2G_ITSSI_SHIFT 8 +#define SIBA_SPROM4_2G_PA_0 0x02 /* 2 GHz power amp */ +#define SIBA_SPROM4_2G_PA_1 0x04 +#define SIBA_SPROM4_2G_PA_2 0x06 +#define SIBA_SPROM4_2G_PA_3 0x08 +#define SIBA_SPROM4_5G_MAXP_ITSSI 0x0A /* 5 GHz ITSSI and 5.3 GHz Max Power */ +#define SIBA_SPROM4_5G_MAXP 0x00FF +#define SIBA_SPROM4_5G_ITSSI 0xFF00 +#define SIBA_SPROM4_5G_ITSSI_SHIFT 8 +#define SIBA_SPROM4_5GHL_MAXP 0x0C /* 5.2 GHz and 5.8 GHz Max Power */ +#define SIBA_SPROM4_5GH_MAXP 0x00FF +#define SIBA_SPROM4_5GL_MAXP 0xFF00 +#define SIBA_SPROM4_5GL_MAXP_SHIFT 8 +#define SIBA_SPROM4_5G_PA_0 0x0E /* 5.3 GHz power amp */ +#define SIBA_SPROM4_5G_PA_1 0x10 +#define SIBA_SPROM4_5G_PA_2 0x12 +#define SIBA_SPROM4_5G_PA_3 0x14 +#define SIBA_SPROM4_5GL_PA_0 0x16 /* 5.2 GHz power amp */ +#define SIBA_SPROM4_5GL_PA_1 0x18 +#define SIBA_SPROM4_5GL_PA_2 0x1A +#define SIBA_SPROM4_5GL_PA_3 0x1C +#define SIBA_SPROM4_5GH_PA_0 0x1E /* 5.8 GHz power amp */ +#define SIBA_SPROM4_5GH_PA_1 0x20 +#define SIBA_SPROM4_5GH_PA_2 0x22 +#define SIBA_SPROM4_5GH_PA_3 0x24 + #define SIBA_SPROM5_BFLOW 0x104a #define SIBA_SPROM5_BFHIGH 0x104c #define SIBA_SPROM5_MAC_80211BG 0x1052 @@ -374,6 +414,7 @@ #define SIBA_SPROM5_GPIOB 0x1078 #define SIBA_SPROM5_GPIOB_P2 0x00ff #define SIBA_SPROM5_GPIOB_P3 0xff00 + #define SIBA_SPROM8_BFLOW 0x1084 #define SIBA_SPROM8_BFHIGH 0x1086 #define SIBA_SPROM8_BFL2LO 0x1088 @@ -414,6 +455,8 @@ #define SIBA_SPROM8_RXPO 0x10ac #define SIBA_SPROM8_RXPO2G 0x00ff #define SIBA_SPROM8_RXPO5G 0xff00 + +/* The FEM blocks share the same structure */ #define SIBA_SPROM8_FEM2G 0x00AE #define SIBA_SPROM8_FEM5G 0x00B0 #define SSB_SROM8_FEM_TSSIPOS 0x0001 @@ -421,6 +464,7 @@ #define SSB_SROM8_FEM_PDET_RANGE 0x00F8 #define SSB_SROM8_FEM_TR_ISO 0x0700 #define SSB_SROM8_FEM_ANTSWLUT 0xF800 + #define SIBA_SPROM8_MAXP_BG 0x10c0 #define SIBA_SPROM8_MAXP_BG_MASK 0x00ff #define SIBA_SPROM8_TSSI_BG 0xff00 @@ -448,12 +492,44 @@ #define SIBA_SPROM8_OFDM5GLPO 0x114a #define SIBA_SPROM8_OFDM5GHPO 0x114e +/* There are 4 blocks with power info sharing the same layout */ +#define SIBA_SROM8_PWR_INFO_CORE0 0x00C0 +#define SIBA_SROM8_PWR_INFO_CORE1 0x00E0 +#define SIBA_SROM8_PWR_INFO_CORE2 0x0100 +#define SIBA_SROM8_PWR_INFO_CORE3 0x0120 + +#define SIBA_SROM8_2G_MAXP_ITSSI 0x00 +#define SIBA_SPROM8_2G_MAXP 0x00FF +#define SIBA_SPROM8_2G_ITSSI 0xFF00 +#define SIBA_SPROM8_2G_ITSSI_SHIFT 8 +#define SIBA_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */ +#define SIBA_SROM8_2G_PA_1 0x04 +#define SIBA_SROM8_2G_PA_2 0x06 +#define SIBA_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */ +#define SIBA_SPROM8_5G_MAXP 0x00FF +#define SIBA_SPROM8_5G_ITSSI 0xFF00 +#define SIBA_SPROM8_5G_ITSSI_SHIFT 8 +#define SIBA_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */ +#define SIBA_SPROM8_5GH_MAXP 0x00FF +#define SIBA_SPROM8_5GL_MAXP 0xFF00 +#define SIBA_SPROM8_5GL_MAXP_SHIFT 8 +#define SIBA_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */ +#define SIBA_SROM8_5G_PA_1 0x0E +#define SIBA_SROM8_5G_PA_2 0x10 +#define SIBA_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */ +#define SIBA_SROM8_5GL_PA_1 0x14 +#define SIBA_SROM8_5GL_PA_2 0x16 +#define SIBA_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */ +#define SIBA_SROM8_5GH_PA_1 0x1A +#define SIBA_SROM8_5GH_PA_2 0x1C + #define SIBA_BOARDVENDOR_DELL 0x1028 #define SIBA_BOARDVENDOR_BCM 0x14e4 #define SIBA_BOARD_BCM4309G 0x0421 #define SIBA_BOARD_MP4318 0x044a #define SIBA_BOARD_BU4306 0x0416 #define SIBA_BOARD_BU4309 0x040a +#define SIBA_BOARD_BCM4321 0x046d #define SIBA_PCICORE_BCAST_ADDR SIBA_CC_BCAST_ADDR #define SIBA_PCICORE_BCAST_DATA SIBA_CC_BCAST_DATA Modified: head/sys/dev/siba/sibavar.h ============================================================================== --- head/sys/dev/siba/sibavar.h Wed May 11 06:27:00 2016 (r299408) +++ head/sys/dev/siba/sibavar.h Wed May 11 06:27:46 2016 (r299409) @@ -389,6 +389,12 @@ SIBA_SPROM_ACCESSOR(fem_5ghz_antswlut, F #undef SIBA_SPROM_ACCESSOR +struct siba_sprom_core_pwr_info { + uint8_t itssi_2g, itssi_5g; + uint8_t maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh; + uint8_t pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4]; +}; + struct siba_sprom { uint8_t rev; /* revision */ uint8_t mac_80211bg[6]; /* address for 802.11b/g */ @@ -448,6 +454,8 @@ struct siba_sprom { uint16_t bf2_lo; uint16_t bf2_hi; + struct siba_sprom_core_pwr_info core_pwr_info[4]; + struct { struct { int8_t a0, a1, a2, a3; @@ -601,5 +609,7 @@ void siba_cc_pmu_set_ldoparef(device_t, void siba_gpio_set(device_t, uint32_t); uint32_t siba_gpio_get(device_t); void siba_fix_imcfglobug(device_t); +int siba_sprom_get_core_power_info(device_t, int, + struct siba_sprom_core_pwr_info *); #endif /* _SIBA_SIBAVAR_H_ */
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