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Date:      Thu, 8 Mar 2018 10:43:42 +0000 (UTC)
From:      Hans Petter Selasky <hselasky@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r330647 - in head/sys/dev/mlx5: . mlx5_core mlx5_en mlx5_ib
Message-ID:  <201803081043.w28Ahg6E060905@repo.freebsd.org>

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Author: hselasky
Date: Thu Mar  8 10:43:42 2018
New Revision: 330647
URL: https://svnweb.freebsd.org/changeset/base/330647

Log:
  Use the autogenerated interface file for all commands in mlx5core.
  
  This patch accumulates the following Linux commits:
  - 90b3e38d048f09b22fb50bcd460cea65fd00b2d7
    mlx5_core: Modify CQ moderation parameters
  - 09a7d9eca1a6cf5eb4f9abfdf8914db9dbd96f08
    mlx5_core: QP/XRCD commands via mlx5 ifc
  - 1a412fb1caa2c1b77719ccb5ed8b0c3c2bc65da7
    mlx5_core: Modify QP commands via mlx5 ifc
  - ec22eb53106be1472ba6573dc900943f52f8fd1e
    mlx5_core: MKey/PSV commands via mlx5 ifc
  - 73b626c182dff06867ceba996a819e8372c9b2ce
    mlx5_core: EQ commands via mlx5 ifc
  - 20ed51c643b6296789a48adc3bc2cc875a1612cf
    mlx5_core: Access register and MAD IFC commands via mlx5 ifc
  - a533ed5e179cd15512d40282617909d3482a771c
    mlx5_core: Pages management commands via mlx5 ifc
  - b8a4ddb2e8f44f872fb93bbda2d541b27079fd2b
    mlx5_core: Add MLX5_ARRAY_SET64 to fix BUILD_BUG_ON
  - af1ba291c5e498973cc325c501dd8da80b234571
    mlx5_core: Refactor internal SRQ API
  - b06e7de8a9d8d1d540ec122bbdf2face2a211634
    mlx5_core: Refactor device capability function
  - c4f287c4a6ac489c18afc4acc4353141a8c53070
    mlx5_core: Unify and improve command interface
  
  Submitted by:	Matthew Finlay <matt@mellanox.com>
  MFC after:	1 week
  Sponsored by:	Mellanox Technologies

Modified:
  head/sys/dev/mlx5/cq.h
  head/sys/dev/mlx5/device.h
  head/sys/dev/mlx5/driver.h
  head/sys/dev/mlx5/mlx5_core/mlx5_cmd.c
  head/sys/dev/mlx5/mlx5_core/mlx5_core.h
  head/sys/dev/mlx5/mlx5_core/mlx5_cq.c
  head/sys/dev/mlx5/mlx5_core/mlx5_eq.c
  head/sys/dev/mlx5/mlx5_core/mlx5_fs_cmd.c
  head/sys/dev/mlx5/mlx5_core/mlx5_fw.c
  head/sys/dev/mlx5/mlx5_core/mlx5_mad.c
  head/sys/dev/mlx5/mlx5_core/mlx5_main.c
  head/sys/dev/mlx5/mlx5_core/mlx5_mcg.c
  head/sys/dev/mlx5/mlx5_core/mlx5_mr.c
  head/sys/dev/mlx5/mlx5_core/mlx5_pagealloc.c
  head/sys/dev/mlx5/mlx5_core/mlx5_pd.c
  head/sys/dev/mlx5/mlx5_core/mlx5_port.c
  head/sys/dev/mlx5/mlx5_core/mlx5_qp.c
  head/sys/dev/mlx5/mlx5_core/mlx5_srq.c
  head/sys/dev/mlx5/mlx5_core/mlx5_transobj.c
  head/sys/dev/mlx5/mlx5_core/mlx5_uar.c
  head/sys/dev/mlx5/mlx5_core/mlx5_vport.c
  head/sys/dev/mlx5/mlx5_en/mlx5_en_main.c
  head/sys/dev/mlx5/mlx5_ib/mlx5_ib_cq.c
  head/sys/dev/mlx5/mlx5_ib/mlx5_ib_mr.c
  head/sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c
  head/sys/dev/mlx5/mlx5_ib/mlx5_ib_srq.c
  head/sys/dev/mlx5/mlx5_ifc.h
  head/sys/dev/mlx5/qp.h
  head/sys/dev/mlx5/srq.h

Modified: head/sys/dev/mlx5/cq.h
==============================================================================
--- head/sys/dev/mlx5/cq.h	Thu Mar  8 09:58:41 2018	(r330646)
+++ head/sys/dev/mlx5/cq.h	Thu Mar  8 10:43:42 2018	(r330647)
@@ -157,12 +157,12 @@ static inline void mlx5_cq_arm(struct mlx5_core_cq *cq
 int mlx5_init_cq_table(struct mlx5_core_dev *dev);
 void mlx5_cleanup_cq_table(struct mlx5_core_dev *dev);
 int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
-			struct mlx5_create_cq_mbox_in *in, int inlen);
+			u32 *in, int inlen);
 int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
 int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
-		       struct mlx5_query_cq_mbox_out *out);
+		       u32 *out, int outlen);
 int mlx5_core_modify_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
-			struct mlx5_modify_cq_mbox_in *in, int in_sz);
+			u32 *in, int inlen);
 int mlx5_core_modify_cq_moderation(struct mlx5_core_dev *dev,
 				   struct mlx5_core_cq *cq, u16 cq_period,
 				   u16 cq_max_count);

Modified: head/sys/dev/mlx5/device.h
==============================================================================
--- head/sys/dev/mlx5/device.h	Thu Mar  8 09:58:41 2018	(r330646)
+++ head/sys/dev/mlx5/device.h	Thu Mar  8 10:43:42 2018	(r330647)
@@ -92,12 +92,21 @@ __mlx5_mask(typ, fld))
 	___t; \
 })
 
-#define MLX5_SET64(typ, p, fld, v) do { \
+#define __MLX5_SET64(typ, p, fld, v) do { \
 	BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
-	BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
 	*((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
 } while (0)
 
+#define MLX5_SET64(typ, p, fld, v) do { \
+	BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
+	__MLX5_SET64(typ, p, fld, v); \
+} while (0)
+
+#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
+	BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
+	__MLX5_SET64(typ, p, fld[idx], v); \
+} while (0)
+
 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
 
 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
@@ -366,30 +375,6 @@ enum {
 	MLX5_MAX_SGE_RD	= (512 - 16 - 16) / 16
 };
 
-struct mlx5_inbox_hdr {
-	__be16		opcode;
-	u8		rsvd[4];
-	__be16		opmod;
-};
-
-struct mlx5_outbox_hdr {
-	u8		status;
-	u8		rsvd[3];
-	__be32		syndrome;
-};
-
-struct mlx5_cmd_set_dc_cnak_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	u8			enable;
-	u8			reserved[47];
-	__be64			pa;
-};
-
-struct mlx5_cmd_set_dc_cnak_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	u8			rsvd[8];
-};
-
 struct mlx5_cmd_layout {
 	u8		type;
 	u8		rsvd0[3];
@@ -405,7 +390,6 @@ struct mlx5_cmd_layout {
 	u8		status_own;
 };
 
-
 struct mlx5_health_buffer {
 	__be32		assert_var[5];
 	__be32		rsvd0[3];
@@ -736,211 +720,6 @@ struct mlx5_cqe128 {
 	struct mlx5_cqe64	cqe64;
 };
 
-struct mlx5_srq_ctx {
-	u8			state_log_sz;
-	u8			rsvd0[3];
-	__be32			flags_xrcd;
-	__be32			pgoff_cqn;
-	u8			rsvd1[4];
-	u8			log_pg_sz;
-	u8			rsvd2[7];
-	__be32			pd;
-	__be16			lwm;
-	__be16			wqe_cnt;
-	u8			rsvd3[8];
-	__be64			db_record;
-};
-
-struct mlx5_create_srq_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	__be32			input_srqn;
-	u8			rsvd0[4];
-	struct mlx5_srq_ctx	ctx;
-	u8			rsvd1[208];
-	__be64			pas[0];
-};
-
-struct mlx5_create_srq_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	__be32			srqn;
-	u8			rsvd[4];
-};
-
-struct mlx5_destroy_srq_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	__be32			srqn;
-	u8			rsvd[4];
-};
-
-struct mlx5_destroy_srq_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	u8			rsvd[8];
-};
-
-struct mlx5_query_srq_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	__be32			srqn;
-	u8			rsvd0[4];
-};
-
-struct mlx5_query_srq_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	u8			rsvd0[8];
-	struct mlx5_srq_ctx	ctx;
-	u8			rsvd1[32];
-	__be64			pas[0];
-};
-
-struct mlx5_arm_srq_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	__be32			srqn;
-	__be16			rsvd;
-	__be16			lwm;
-};
-
-struct mlx5_arm_srq_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	u8			rsvd[8];
-};
-
-struct mlx5_cq_context {
-	u8			status;
-	u8			cqe_sz_flags;
-	u8			st;
-	u8			rsvd3;
-	u8			rsvd4[6];
-	__be16			page_offset;
-	__be32			log_sz_usr_page;
-	__be16			cq_period;
-	__be16			cq_max_count;
-	__be16			rsvd20;
-	__be16			c_eqn;
-	u8			log_pg_sz;
-	u8			rsvd25[7];
-	__be32			last_notified_index;
-	__be32			solicit_producer_index;
-	__be32			consumer_counter;
-	__be32			producer_counter;
-	u8			rsvd48[8];
-	__be64			db_record_addr;
-};
-
-struct mlx5_create_cq_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	__be32			input_cqn;
-	u8			rsvdx[4];
-	struct mlx5_cq_context	ctx;
-	u8			rsvd6[192];
-	__be64			pas[0];
-};
-
-struct mlx5_create_cq_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	__be32			cqn;
-	u8			rsvd0[4];
-};
-
-struct mlx5_destroy_cq_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	__be32			cqn;
-	u8			rsvd0[4];
-};
-
-struct mlx5_destroy_cq_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	u8			rsvd0[8];
-};
-
-struct mlx5_query_cq_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	__be32			cqn;
-	u8			rsvd0[4];
-};
-
-struct mlx5_query_cq_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	u8			rsvd0[8];
-	struct mlx5_cq_context	ctx;
-	u8			rsvd6[16];
-	__be64			pas[0];
-};
-
-struct mlx5_modify_cq_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	__be32			cqn;
-	__be32			field_select;
-	struct mlx5_cq_context	ctx;
-	u8			rsvd[192];
-	__be64			pas[0];
-};
-
-struct mlx5_modify_cq_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	u8			rsvd[8];
-};
-
-struct mlx5_eq_context {
-	u8			status;
-	u8			ec_oi;
-	u8			st;
-	u8			rsvd2[7];
-	__be16			page_pffset;
-	__be32			log_sz_usr_page;
-	u8			rsvd3[7];
-	u8			intr;
-	u8			log_page_size;
-	u8			rsvd4[15];
-	__be32			consumer_counter;
-	__be32			produser_counter;
-	u8			rsvd5[16];
-};
-
-struct mlx5_create_eq_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	u8			rsvd0[3];
-	u8			input_eqn;
-	u8			rsvd1[4];
-	struct mlx5_eq_context	ctx;
-	u8			rsvd2[8];
-	__be64			events_mask;
-	u8			rsvd3[176];
-	__be64			pas[0];
-};
-
-struct mlx5_create_eq_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	u8			rsvd0[3];
-	u8			eq_number;
-	u8			rsvd1[4];
-};
-
-struct mlx5_map_eq_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	__be64			mask;
-	u8			mu;
-	u8			rsvd0[2];
-	u8			eqn;
-	u8			rsvd1[24];
-};
-
-struct mlx5_map_eq_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	u8			rsvd[8];
-};
-
-struct mlx5_query_eq_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	u8			rsvd0[3];
-	u8			eqn;
-	u8			rsvd1[4];
-};
-
-struct mlx5_query_eq_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	u8			rsvd[8];
-	struct mlx5_eq_context	ctx;
-};
-
 enum {
 	MLX5_MKEY_STATUS_FREE = 1 << 6,
 };
@@ -967,121 +746,10 @@ struct mlx5_mkey_seg {
 	u8		rsvd4[4];
 };
 
-struct mlx5_query_special_ctxs_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	u8			rsvd[8];
-};
-
-struct mlx5_query_special_ctxs_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	__be32			dump_fill_mkey;
-	__be32			reserved_lkey;
-};
-
-struct mlx5_create_mkey_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	__be32			input_mkey_index;
-	__be32			flags;
-	struct mlx5_mkey_seg	seg;
-	u8			rsvd1[16];
-	__be32			xlat_oct_act_size;
-	__be32			rsvd2;
-	u8			rsvd3[168];
-	__be64			pas[0];
-};
-
-struct mlx5_create_mkey_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	__be32			mkey;
-	u8			rsvd[4];
-};
-
-struct mlx5_query_mkey_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	__be32			mkey;
-};
-
-struct mlx5_query_mkey_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	__be64			pas[0];
-};
-
-struct mlx5_modify_mkey_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	__be32			mkey;
-	__be64			pas[0];
-};
-
-struct mlx5_modify_mkey_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	u8			rsvd[8];
-};
-
-struct mlx5_dump_mkey_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-};
-
-struct mlx5_dump_mkey_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	__be32			mkey;
-};
-
-struct mlx5_mad_ifc_mbox_in {
-	struct mlx5_inbox_hdr	hdr;
-	__be16			remote_lid;
-	u8			rsvd0;
-	u8			port;
-	u8			rsvd1[4];
-	u8			data[256];
-};
-
-struct mlx5_mad_ifc_mbox_out {
-	struct mlx5_outbox_hdr	hdr;
-	u8			rsvd[8];
-	u8			data[256];
-};
-
-struct mlx5_access_reg_mbox_in {
-	struct mlx5_inbox_hdr		hdr;
-	u8				rsvd0[2];
-	__be16				register_id;
-	__be32				arg;
-	__be32				data[0];
-};
-
-struct mlx5_access_reg_mbox_out {
-	struct mlx5_outbox_hdr		hdr;
-	u8				rsvd[8];
-	__be32				data[0];
-};
-
 #define MLX5_ATTR_EXTENDED_PORT_INFO	cpu_to_be16(0xff90)
 
 enum {
 	MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO	= 1 <<  0
-};
-
-struct mlx5_allocate_psv_in {
-	struct mlx5_inbox_hdr   hdr;
-	__be32			npsv_pd;
-	__be32			rsvd_psv0;
-};
-
-struct mlx5_allocate_psv_out {
-	struct mlx5_outbox_hdr  hdr;
-	u8			rsvd[8];
-	__be32			psv_idx[4];
-};
-
-struct mlx5_destroy_psv_in {
-	struct mlx5_inbox_hdr	hdr;
-	__be32                  psv_number;
-	u8                      rsvd[4];
-};
-
-struct mlx5_destroy_psv_out {
-	struct mlx5_outbox_hdr  hdr;
-	u8                      rsvd[8];
 };
 
 static inline int mlx5_host_is_le(void)

Modified: head/sys/dev/mlx5/driver.h
==============================================================================
--- head/sys/dev/mlx5/driver.h	Thu Mar  8 09:58:41 2018	(r330646)
+++ head/sys/dev/mlx5/driver.h	Thu Mar  8 10:43:42 2018	(r330647)
@@ -41,6 +41,7 @@
 
 #include <dev/mlx5/device.h>
 #include <dev/mlx5/doorbell.h>
+#include <dev/mlx5/srq.h>
 
 #define MLX5_QCOUNTER_SETS_NETDEV 64
 #define MLX5_MAX_NUMBER_OF_VFS 128
@@ -856,10 +857,8 @@ int mlx5_cmd_init(struct mlx5_core_dev *dev);
 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
-int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
-int mlx5_cmd_status_to_err_v2(void *ptr);
-int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
-		       enum mlx5_cap_mode cap_mode);
+void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
+int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
 		  int out_size);
 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
@@ -883,23 +882,26 @@ int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size
 		   struct mlx5_buf *buf);
 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
-			 struct mlx5_create_srq_mbox_in *in, int inlen,
-			 int is_xrc);
+			 struct mlx5_srq_attr *in);
 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
-			struct mlx5_query_srq_mbox_out *out);
+			struct mlx5_srq_attr *out);
 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
 		      u16 lwm, int is_srq);
 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
-int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
-			  struct mlx5_create_mkey_mbox_in *in, int inlen,
-			  mlx5_cmd_cbk_t callback, void *context,
-			  struct mlx5_create_mkey_mbox_out *out);
-int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
-int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
-			 struct mlx5_query_mkey_mbox_out *out, int outlen);
+int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
+			     struct mlx5_core_mr *mkey,
+			     u32 *in, int inlen,
+			     u32 *out, int outlen,
+			     mlx5_cmd_cbk_t callback, void *context);
+int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
+			  struct mlx5_core_mr *mr,
+			  u32 *in, int inlen);
+int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey);
+int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey,
+			 u32 *out, int outlen);
 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
 			     u32 *mkey);
 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
@@ -954,7 +956,7 @@ void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
-		       struct mlx5_query_eq_mbox_out *out, int outlen);
+		       u32 *out, int outlen);
 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);

Modified: head/sys/dev/mlx5/mlx5_core/mlx5_cmd.c
==============================================================================
--- head/sys/dev/mlx5/mlx5_core/mlx5_cmd.c	Thu Mar  8 09:58:41 2018	(r330646)
+++ head/sys/dev/mlx5/mlx5_core/mlx5_cmd.c	Thu Mar  8 10:43:42 2018	(r330647)
@@ -75,6 +75,26 @@ enum {
 	MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR		= 0x10,
 };
 
+struct mlx5_ifc_mbox_out_bits {
+	u8	   status[0x8];
+	u8	   reserved_at_8[0x18];
+
+	u8	   syndrome[0x20];
+
+	u8	   reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_mbox_in_bits {
+	u8	   opcode[0x10];
+	u8	   reserved_at_10[0x10];
+
+	u8	   reserved_at_20[0x10];
+	u8	   op_mod[0x10];
+
+	u8	   reserved_at_40[0x40];
+};
+
+
 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
 					   struct mlx5_cmd_msg *in,
 					   int uin_size,
@@ -588,11 +608,105 @@ const char *mlx5_command_str(int command)
 	}
 }
 
+static const char *cmd_status_str(u8 status)
+{
+	switch (status) {
+	case MLX5_CMD_STAT_OK:
+		return "OK";
+	case MLX5_CMD_STAT_INT_ERR:
+		return "internal error";
+	case MLX5_CMD_STAT_BAD_OP_ERR:
+		return "bad operation";
+	case MLX5_CMD_STAT_BAD_PARAM_ERR:
+		return "bad parameter";
+	case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
+		return "bad system state";
+	case MLX5_CMD_STAT_BAD_RES_ERR:
+		return "bad resource";
+	case MLX5_CMD_STAT_RES_BUSY:
+		return "resource busy";
+	case MLX5_CMD_STAT_LIM_ERR:
+		return "limits exceeded";
+	case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
+		return "bad resource state";
+	case MLX5_CMD_STAT_IX_ERR:
+		return "bad index";
+	case MLX5_CMD_STAT_NO_RES_ERR:
+		return "no resources";
+	case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
+		return "bad input length";
+	case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
+		return "bad output length";
+	case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
+		return "bad QP state";
+	case MLX5_CMD_STAT_BAD_PKT_ERR:
+		return "bad packet (discarded)";
+	case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
+		return "bad size too many outstanding CQEs";
+	default:
+		return "unknown status";
+	}
+}
+
+static int cmd_status_to_err_helper(u8 status)
+{
+	switch (status) {
+	case MLX5_CMD_STAT_OK:				return 0;
+	case MLX5_CMD_STAT_INT_ERR:			return -EIO;
+	case MLX5_CMD_STAT_BAD_OP_ERR:			return -EINVAL;
+	case MLX5_CMD_STAT_BAD_PARAM_ERR:		return -EINVAL;
+	case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:		return -EIO;
+	case MLX5_CMD_STAT_BAD_RES_ERR:			return -EINVAL;
+	case MLX5_CMD_STAT_RES_BUSY:			return -EBUSY;
+	case MLX5_CMD_STAT_LIM_ERR:			return -ENOMEM;
+	case MLX5_CMD_STAT_BAD_RES_STATE_ERR:		return -EINVAL;
+	case MLX5_CMD_STAT_IX_ERR:			return -EINVAL;
+	case MLX5_CMD_STAT_NO_RES_ERR:			return -EAGAIN;
+	case MLX5_CMD_STAT_BAD_INP_LEN_ERR:		return -EIO;
+	case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:		return -EIO;
+	case MLX5_CMD_STAT_BAD_QP_STATE_ERR:		return -EINVAL;
+	case MLX5_CMD_STAT_BAD_PKT_ERR:			return -EINVAL;
+	case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:	return -EINVAL;
+	default:					return -EIO;
+	}
+}
+
+void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
+{
+	*status = MLX5_GET(mbox_out, out, status);
+	*syndrome = MLX5_GET(mbox_out, out, syndrome);
+}
+
+static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
+{
+	u32 syndrome;
+	u8  status;
+	u16 opcode;
+	u16 op_mod;
+
+	mlx5_cmd_mbox_status(out, &status, &syndrome);
+	if (!status)
+		return 0;
+
+	opcode = MLX5_GET(mbox_in, in, opcode);
+	op_mod = MLX5_GET(mbox_in, in, op_mod);
+
+	mlx5_core_err(dev,
+		      "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
+		       mlx5_command_str(opcode),
+		       opcode, op_mod,
+		       cmd_status_str(status),
+		       status,
+		       syndrome);
+
+	return cmd_status_to_err_helper(status);
+}
+
 static void dump_command(struct mlx5_core_dev *dev,
 			 struct mlx5_cmd_work_ent *ent, int input)
 {
-	u16 op = be16_to_cpu(((struct mlx5_inbox_hdr *)(ent->lay->in))->opcode);
 	struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
+	u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
 	size_t i;
 	int data_only;
 	int offset = 0;
@@ -654,9 +768,7 @@ static void dump_command(struct mlx5_core_dev *dev,
 
 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 {
-        struct mlx5_inbox_hdr *hdr = (struct mlx5_inbox_hdr *)(in->first.data);
-
-        return be16_to_cpu(hdr->opcode);
+	return MLX5_GET(mbox_in, in->first.data, opcode);
 }
 
 static void cb_timeout_handler(struct work_struct *work)
@@ -676,173 +788,6 @@ static void cb_timeout_handler(struct work_struct *wor
         mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
 }
 
-static int set_internal_err_outbox(struct mlx5_core_dev *dev, u16 opcode,
-				   struct mlx5_outbox_hdr *hdr)
-{
-	hdr->status = 0;
-	hdr->syndrome = 0;
-
-	switch (opcode) {
-	case MLX5_CMD_OP_TEARDOWN_HCA:
-	case MLX5_CMD_OP_DISABLE_HCA:
-	case MLX5_CMD_OP_MANAGE_PAGES:
-	case MLX5_CMD_OP_DESTROY_MKEY:
-	case MLX5_CMD_OP_DESTROY_EQ:
-	case MLX5_CMD_OP_DESTROY_CQ:
-	case MLX5_CMD_OP_DESTROY_QP:
-	case MLX5_CMD_OP_DESTROY_PSV:
-	case MLX5_CMD_OP_DESTROY_SRQ:
-	case MLX5_CMD_OP_DESTROY_XRC_SRQ:
-	case MLX5_CMD_OP_DESTROY_DCT:
-	case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
-	case MLX5_CMD_OP_DEALLOC_PD:
-	case MLX5_CMD_OP_DEALLOC_UAR:
-	case MLX5_CMD_OP_DETACH_FROM_MCG:
-	case MLX5_CMD_OP_DEALLOC_XRCD:
-	case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
-	case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
-	case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
-	case MLX5_CMD_OP_DESTROY_LAG:
-	case MLX5_CMD_OP_DESTROY_VPORT_LAG:
-	case MLX5_CMD_OP_DESTROY_TIR:
-	case MLX5_CMD_OP_DESTROY_SQ:
-	case MLX5_CMD_OP_DESTROY_RQ:
-	case MLX5_CMD_OP_DESTROY_RMP:
-	case MLX5_CMD_OP_DESTROY_TIS:
-	case MLX5_CMD_OP_DESTROY_RQT:
-	case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
-	case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
-	case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
-	case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
-	case MLX5_CMD_OP_2ERR_QP:
-	case MLX5_CMD_OP_2RST_QP:
-	case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
-	case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
-	case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
-	case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
-	case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
-	case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
-	case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
-	case MLX5_CMD_OP_MODIFY_VPORT_STATE:
-	case MLX5_CMD_OP_MODIFY_SQ:
-	case MLX5_CMD_OP_MODIFY_RQ:
-	case MLX5_CMD_OP_MODIFY_TIS:
-	case MLX5_CMD_OP_MODIFY_LAG:
-	case MLX5_CMD_OP_MODIFY_TIR:
-	case MLX5_CMD_OP_MODIFY_RMP:
-	case MLX5_CMD_OP_MODIFY_RQT:
-	case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
-	case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
-	case MLX5_CMD_OP_MODIFY_CONG_STATUS:
-	case MLX5_CMD_OP_MODIFY_CQ:
-	case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
-	case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
-	case MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP:
-	case MLX5_CMD_OP_ACCESS_REG:
-	case MLX5_CMD_OP_DRAIN_DCT:
-		return 0;
-
-	case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
-	case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
-	case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
-	case MLX5_CMD_OP_ALLOC_PD:
-	case MLX5_CMD_OP_ALLOC_Q_COUNTER:
-	case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
-	case MLX5_CMD_OP_ALLOC_UAR:
-	case MLX5_CMD_OP_ALLOC_XRCD:
-	case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
-	case MLX5_CMD_OP_ARM_RQ:
-	case MLX5_CMD_OP_ARM_XRC_SRQ:
-	case MLX5_CMD_OP_ATTACH_TO_MCG:
-	case MLX5_CMD_OP_CONFIG_INT_MODERATION:
-	case MLX5_CMD_OP_CREATE_CQ:
-	case MLX5_CMD_OP_CREATE_DCT:
-	case MLX5_CMD_OP_CREATE_EQ:
-	case MLX5_CMD_OP_CREATE_FLOW_GROUP:
-	case MLX5_CMD_OP_CREATE_FLOW_TABLE:
-	case MLX5_CMD_OP_CREATE_LAG:
-	case MLX5_CMD_OP_CREATE_MKEY:
-	case MLX5_CMD_OP_CREATE_PSV:
-	case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
-	case MLX5_CMD_OP_CREATE_QP:
-	case MLX5_CMD_OP_CREATE_RMP:
-	case MLX5_CMD_OP_CREATE_RQ:
-	case MLX5_CMD_OP_CREATE_RQT:
-	case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
-	case MLX5_CMD_OP_CREATE_SQ:
-	case MLX5_CMD_OP_CREATE_SRQ:
-	case MLX5_CMD_OP_CREATE_TIR:
-	case MLX5_CMD_OP_CREATE_TIS:
-	case MLX5_CMD_OP_CREATE_VPORT_LAG:
-	case MLX5_CMD_OP_CREATE_XRC_SRQ:
-	case MLX5_CMD_OP_ENABLE_HCA:
-	case MLX5_CMD_OP_GEN_EQE:
-	case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
-	case MLX5_CMD_OP_INIT2INIT_QP:
-	case MLX5_CMD_OP_INIT2RTR_QP:
-	case MLX5_CMD_OP_INIT_HCA:
-	case MLX5_CMD_OP_MAD_IFC:
-	case MLX5_CMD_OP_NOP:
-	case MLX5_CMD_OP_PAGE_FAULT_RESUME:
-	case MLX5_CMD_OP_QUERY_ADAPTER:
-	case MLX5_CMD_OP_QUERY_CONG_PARAMS:
-	case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
-	case MLX5_CMD_OP_QUERY_CONG_STATUS:
-	case MLX5_CMD_OP_QUERY_CQ:
-	case MLX5_CMD_OP_QUERY_DCT:
-	case MLX5_CMD_OP_QUERY_EQ:
-	case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
-	case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
-	case MLX5_CMD_OP_QUERY_FLOW_GROUP:
-	case MLX5_CMD_OP_QUERY_FLOW_TABLE:
-	case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
-	case MLX5_CMD_OP_QUERY_HCA_CAP:
-	case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
-	case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
-	case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
-	case MLX5_CMD_OP_QUERY_ISSI:
-	case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
-	case MLX5_CMD_OP_QUERY_LAG:
-	case MLX5_CMD_OP_QUERY_MAD_DEMUX:
-	case MLX5_CMD_OP_QUERY_MKEY:
-	case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
-	case MLX5_CMD_OP_QUERY_OTHER_HCA_CAP:
-	case MLX5_CMD_OP_QUERY_PAGES:
-	case MLX5_CMD_OP_QUERY_QP:
-	case MLX5_CMD_OP_QUERY_Q_COUNTER:
-	case MLX5_CMD_OP_QUERY_RMP:
-	case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
-	case MLX5_CMD_OP_QUERY_RQ:
-	case MLX5_CMD_OP_QUERY_RQT:
-	case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
-	case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
-	case MLX5_CMD_OP_QUERY_SQ:
-	case MLX5_CMD_OP_QUERY_SRQ:
-	case MLX5_CMD_OP_QUERY_TIR:
-	case MLX5_CMD_OP_QUERY_TIS:
-	case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
-	case MLX5_CMD_OP_QUERY_VPORT_STATE:
-	case MLX5_CMD_OP_QUERY_XRC_SRQ:
-	case MLX5_CMD_OP_RST2INIT_QP:
-	case MLX5_CMD_OP_RTR2RTS_QP:
-	case MLX5_CMD_OP_RTS2RTS_QP:
-	case MLX5_CMD_OP_SET_DC_CNAK_TRACE:
-	case MLX5_CMD_OP_SET_HCA_CAP:
-	case MLX5_CMD_OP_SET_ISSI:
-	case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
-	case MLX5_CMD_OP_SET_MAD_DEMUX:
-	case MLX5_CMD_OP_SET_ROCE_ADDRESS:
-	case MLX5_CMD_OP_SQD_RTS_QP:
-	case MLX5_CMD_OP_SQERR2RTS_QP:
-		hdr->status = MLX5_CMD_STAT_INT_ERR;
-		hdr->syndrome = 0xFFFFFFFF;
-		return -ECANCELED;
-	default:
-		mlx5_core_err(dev, "Unknown FW command (%d)\n", opcode);
-		return -EINVAL;
-	}
-}
-
 static void complete_command(struct mlx5_cmd_work_ent *ent)
 {
 	struct mlx5_cmd *cmd = ent->cmd;
@@ -863,15 +808,12 @@ static void complete_command(struct mlx5_cmd_work_ent 
 		sem = &cmd->sem;
 
 	if (dev->state != MLX5_DEVICE_STATE_UP) {
-		struct mlx5_outbox_hdr *out_hdr =
-			(struct mlx5_outbox_hdr *)ent->out;
-		struct mlx5_inbox_hdr *in_hdr =
-			(struct mlx5_inbox_hdr *)(ent->in->first.data);
-		u16 opcode = be16_to_cpu(in_hdr->opcode);
+		u8 status = 0;
+		u32 drv_synd;
 
-		ent->ret = set_internal_err_outbox(dev,
-						   opcode,
-						   out_hdr);
+		ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
+		MLX5_SET(mbox_out, ent->out, status, status);
+		MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
 	}
 
 	if (ent->callback) {
@@ -887,10 +829,14 @@ static void complete_command(struct mlx5_cmd_work_ent 
 		callback = ent->callback;
 		context = ent->context;
 		err = ent->ret;
-		if (!err)
+		if (!err) {
 			err = mlx5_copy_from_msg(ent->uout,
 						 ent->out,
 						 ent->uout_size);
+			err = err ? err : mlx5_cmd_check(dev,
+							 ent->in->first.data,
+							 ent->uout);
+		}
 
 		mlx5_free_cmd_msg(dev, ent->out);
 		free_msg(dev, ent->in);
@@ -1014,16 +960,6 @@ static int wait_func(struct mlx5_core_dev *dev, struct
 	return err;
 }
 
-static __be32 *get_synd_ptr(struct mlx5_outbox_hdr *out)
-{
-	return &out->syndrome;
-}
-
-static u8 *get_status_ptr(struct mlx5_outbox_hdr *out)
-{
-	return &out->status;
-}
-
 /*  Notes:
  *    1. Callback functions may not sleep
  *    2. page queue commands do not support asynchrous completion
@@ -1070,7 +1006,7 @@ static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, 
                 goto out;
 
         ds = ent->ts2 - ent->ts1;
-        op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
+	op = MLX5_GET(mbox_in, in->first.data, opcode);
         if (op < ARRAY_SIZE(cmd->stats)) {
                 stats = &cmd->stats[op];
                 spin_lock_irq(&stats->lock);
@@ -1315,16 +1251,11 @@ static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core
 	return msg;
 }
 
-static u16 opcode_from_in(struct mlx5_inbox_hdr *in)
+static int is_manage_pages(void *in)
 {
-	return be16_to_cpu(in->opcode);
+	return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
 }
 
-static int is_manage_pages(struct mlx5_inbox_hdr *in)
-{
-	return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
-}
-
 static int cmd_exec_helper(struct mlx5_core_dev *dev,
 			   void *in, int in_size,
 			   void *out, int out_size,
@@ -1340,9 +1271,10 @@ static int cmd_exec_helper(struct mlx5_core_dev *dev,
 
 	if (pci_channel_offline(dev->pdev) ||
 	    dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
-		err = mlx5_internal_err_ret_value(dev, opcode_from_in(in), &drv_synd, &status);
-		*get_synd_ptr(out) = cpu_to_be32(drv_synd);
-		*get_status_ptr(out) = status;
+		u16 opcode = MLX5_GET(mbox_in, in, opcode);
+		err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
+		MLX5_SET(mbox_out, out, status, status);
+		MLX5_SET(mbox_out, out, syndrome, drv_synd);
 		return err;
 	}
 
@@ -1396,7 +1328,10 @@ out_in:
 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
 		  int out_size)
 {
-	return cmd_exec_helper(dev, in, in_size, out, out_size, NULL, NULL);
+	int err;
+
+	err = cmd_exec_helper(dev, in, in_size, out, out_size, NULL, NULL);
+	return err ? : mlx5_cmd_check(dev, in, out);
 }
 EXPORT_SYMBOL(mlx5_cmd_exec);
 
@@ -1631,94 +1566,3 @@ void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
 	free_cmd_page(dev, cmd);
 }
 EXPORT_SYMBOL(mlx5_cmd_cleanup);
-
-static const char *cmd_status_str(u8 status)
-{
-	switch (status) {
-	case MLX5_CMD_STAT_OK:
-		return "OK";
-	case MLX5_CMD_STAT_INT_ERR:
-		return "internal error";
-	case MLX5_CMD_STAT_BAD_OP_ERR:
-		return "bad operation";
-	case MLX5_CMD_STAT_BAD_PARAM_ERR:
-		return "bad parameter";
-	case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
-		return "bad system state";
-	case MLX5_CMD_STAT_BAD_RES_ERR:
-		return "bad resource";
-	case MLX5_CMD_STAT_RES_BUSY:
-		return "resource busy";
-	case MLX5_CMD_STAT_LIM_ERR:
-		return "limits exceeded";
-	case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
-		return "bad resource state";
-	case MLX5_CMD_STAT_IX_ERR:
-		return "bad index";
-	case MLX5_CMD_STAT_NO_RES_ERR:
-		return "no resources";
-	case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
-		return "bad input length";
-	case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
-		return "bad output length";
-	case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
-		return "bad QP state";
-	case MLX5_CMD_STAT_BAD_PKT_ERR:
-		return "bad packet (discarded)";
-	case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
-		return "bad size too many outstanding CQEs";
-	default:
-		return "unknown status";
-	}
-}
-
-static int cmd_status_to_err_helper(u8 status)
-{
-	switch (status) {
-	case MLX5_CMD_STAT_OK:				return 0;
-	case MLX5_CMD_STAT_INT_ERR:			return -EIO;
-	case MLX5_CMD_STAT_BAD_OP_ERR:			return -EINVAL;
-	case MLX5_CMD_STAT_BAD_PARAM_ERR:		return -EINVAL;
-	case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:		return -EIO;
-	case MLX5_CMD_STAT_BAD_RES_ERR:			return -EINVAL;
-	case MLX5_CMD_STAT_RES_BUSY:			return -EBUSY;
-	case MLX5_CMD_STAT_LIM_ERR:			return -ENOMEM;
-	case MLX5_CMD_STAT_BAD_RES_STATE_ERR:		return -EINVAL;
-	case MLX5_CMD_STAT_IX_ERR:			return -EINVAL;
-	case MLX5_CMD_STAT_NO_RES_ERR:			return -EAGAIN;
-	case MLX5_CMD_STAT_BAD_INP_LEN_ERR:		return -EIO;
-	case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:		return -EIO;
-	case MLX5_CMD_STAT_BAD_QP_STATE_ERR:		return -EINVAL;
-	case MLX5_CMD_STAT_BAD_PKT_ERR:			return -EINVAL;
-	case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:	return -EINVAL;
-	default:					return -EIO;
-	}
-}
-
-/* this will be available till all the commands use set/get macros */
-int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr)
-{
-	if (!hdr->status)
-		return 0;
-
-	printf("mlx5_core: WARN: ""command failed, status %s(0x%x), syndrome 0x%x\n", cmd_status_str(hdr->status), hdr->status, be32_to_cpu(hdr->syndrome));
-
-	return cmd_status_to_err_helper(hdr->status);
-}
-
-int mlx5_cmd_status_to_err_v2(void *ptr)
-{
-	u32	syndrome;
-	u8	status;
-
-	status = be32_to_cpu(*(__be32 *)ptr) >> 24;

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