Date: Wed, 18 Jul 2018 10:33:07 +0000 (UTC) From: Michal Meloun <mmel@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r336454 - in head/sys: arm/arm arm/include conf Message-ID: <201807181033.w6IAX7Ih097220@repo.freebsd.org>
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Author: mmel Date: Wed Jul 18 10:33:07 2018 New Revision: 336454 URL: https://svnweb.freebsd.org/changeset/base/336454 Log: Remove the dead code from ARM cpufunc_* files. The elf trampoline was never been supported for ARMv6 and ARMv7 and was disconnected from kernel build many months ago. MFC after: 2 weeks Deleted: head/sys/arm/arm/cpufunc_asm_arm11.S head/sys/arm/arm/cpufunc_asm_armv6.S Modified: head/sys/arm/arm/cpufunc_asm.S head/sys/arm/arm/cpufunc_asm_armv7.S head/sys/arm/include/cpufunc.h head/sys/conf/Makefile.arm head/sys/conf/files.arm Modified: head/sys/arm/arm/cpufunc_asm.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm.S Wed Jul 18 10:23:30 2018 (r336453) +++ head/sys/arm/arm/cpufunc_asm.S Wed Jul 18 10:33:07 2018 (r336454) @@ -134,26 +134,6 @@ END(cpufunc_control) /* Random odd functions */ -/* - * Function to get the offset of a stored program counter from the - * instruction doing the store. This offset is defined to be the same - * for all STRs and STMs on a given implementation. Code based on - * section 2.4.3 of the ARM ARM (2nd Ed.), with modifications to work - * in 26-bit modes as well. - */ -ENTRY(get_pc_str_offset) - mov ip, sp - stmfd sp!, {fp, ip, lr, pc} - sub fp, ip, #4 - sub sp, sp, #4 - mov r1, pc /* R1 = addr of following STR */ - mov r0, r0 - str pc, [sp] /* [SP] = . + offset */ - ldr r0, [sp] - sub r0, r0, r1 - ldmdb fp, {fp, sp, pc} -END(get_pc_str_offset) - /* Allocate and lock a cacheline for the specified address. */ #define CPWAIT_BRANCH \ Modified: head/sys/arm/arm/cpufunc_asm_armv7.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_armv7.S Wed Jul 18 10:23:30 2018 (r336453) +++ head/sys/arm/arm/cpufunc_asm_armv7.S Wed Jul 18 10:33:07 2018 (r336454) @@ -37,91 +37,8 @@ __FBSDID("$FreeBSD$"); .cpu cortex-a8 -#ifdef ELF_TRAMPOLINE -.Lcoherency_level: - .word _C_LABEL(arm_cache_loc) -.Lcache_type: - .word _C_LABEL(arm_cache_type) -.Lway_mask: - .word 0x3ff -.Lmax_index: - .word 0x7fff - -/* Based on algorithm from ARM Architecture Reference Manual */ -ENTRY(armv7_dcache_wbinv_all) - stmdb sp!, {r4, r5, r6, r7, r8, r9} - - /* Get cache level */ - ldr r0, .Lcoherency_level - ldr r3, [r0] - cmp r3, #0 - beq Finished - /* For each cache level */ - mov r8, #0 -Loop1: - /* Get cache type for given level */ - mov r2, r8, lsl #2 - add r2, r2, r2 - ldr r0, .Lcache_type - ldr r1, [r0, r2] - - /* Get line size */ - and r2, r1, #7 - add r2, r2, #4 - - /* Get number of ways */ - ldr r4, .Lway_mask - ands r4, r4, r1, lsr #3 - clz r5, r4 - - /* Get max index */ - ldr r7, .Lmax_index - ands r7, r7, r1, lsr #13 -Loop2: - mov r9, r4 -Loop3: - mov r6, r8, lsl #1 - orr r6, r6, r9, lsl r5 - orr r6, r6, r7, lsl r2 - - /* Clean and invalidate data cache by way/index */ - mcr CP15_DCCISW(r6) - subs r9, r9, #1 - bge Loop3 - subs r7, r7, #1 - bge Loop2 -Skip: - add r8, r8, #1 - cmp r3, r8 - bne Loop1 -Finished: - dsb - ldmia sp!, {r4, r5, r6, r7, r8, r9} - RET -END(armv7_dcache_wbinv_all) - -ENTRY(armv7_idcache_wbinv_all) - stmdb sp!, {lr} - bl armv7_dcache_wbinv_all -#ifdef SMP - mcr CP15_ICIALLUIS -#else - mcr CP15_ICIALLU -#endif - dsb - isb - ldmia sp!, {lr} - RET -END(armv7_idcache_wbinv_all) -#endif - ENTRY(armv7_cpu_sleep) dsb /* data synchronization barrier */ wfi /* wait for interrupt */ RET END(armv7_cpu_sleep) - -ENTRY(armv7_drain_writebuf) - dsb - RET -END(armv7_drain_writebuf) Modified: head/sys/arm/include/cpufunc.h ============================================================================== --- head/sys/arm/include/cpufunc.h Wed Jul 18 10:23:30 2018 (r336453) +++ head/sys/arm/include/cpufunc.h Wed Jul 18 10:33:07 2018 (r336454) @@ -275,14 +275,9 @@ void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t) void sheeva_l2cache_wbinv_all (void); #endif -#if defined(CPU_MV_PJ4B) -void armv6_idcache_wbinv_all (void); -#endif #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) -void armv7_idcache_wbinv_all (void); void armv7_cpu_sleep (int); void armv7_setup (void); -void armv7_drain_writebuf (void); void cortexa_setup (void); #endif @@ -292,8 +287,6 @@ void pj4bv7_setup (void); #endif #if defined(CPU_ARM1176) -void arm11_drain_writebuf (void); - void arm11x6_setup (void); void arm11x6_sleep (int); /* no ref. for errata */ #endif @@ -457,12 +450,6 @@ intr_restore(register_t s) void set_stackptr (u_int mode, u_int address); u_int get_stackptr (u_int mode); - -/* - * Miscellany - */ - -int get_pc_str_offset (void); /* * CPU functions from locore.S Modified: head/sys/conf/Makefile.arm ============================================================================== --- head/sys/conf/Makefile.arm Wed Jul 18 10:23:30 2018 (r336453) +++ head/sys/conf/Makefile.arm Wed Jul 18 10:33:07 2018 (r336454) @@ -76,9 +76,7 @@ FILES_CPU_FUNC = \ $S/$M/$M/cpufunc_asm_arm9.S \ $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ $S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.S \ - $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv6.S \ - $S/$M/$M/cpufunc_asm_armv7.S + $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S .if ${MACHINE_ARCH:Marmv[67]*} == "" && defined(KERNPHYSADDR) KERNEL_EXTRA=trampoline Modified: head/sys/conf/files.arm ============================================================================== --- head/sys/conf/files.arm Wed Jul 18 10:23:30 2018 (r336453) +++ head/sys/conf/files.arm Wed Jul 18 10:33:07 2018 (r336454) @@ -31,11 +31,9 @@ arm/arm/copystr.S standard arm/arm/cpufunc.c standard arm/arm/cpufunc_asm.S standard arm/arm/cpufunc_asm_arm9.S optional cpu_arm9 | cpu_arm9e -arm/arm/cpufunc_asm_arm11.S optional cpu_arm1176 arm/arm/cpufunc_asm_arm11x6.S optional cpu_arm1176 arm/arm/cpufunc_asm_armv4.S optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_xscale_pxa2x0 | cpu_xscale_81342 arm/arm/cpufunc_asm_armv5_ec.S optional cpu_arm9e -arm/arm/cpufunc_asm_armv6.S optional cpu_arm1176 arm/arm/cpufunc_asm_armv7.S optional cpu_cortexa | cpu_krait | cpu_mv_pj4b arm/arm/cpufunc_asm_fa526.S optional cpu_fa526 arm/arm/cpufunc_asm_pj4b.S optional cpu_mv_pj4b
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