From owner-svn-src-stable-12@freebsd.org Mon Oct 5 18:08:53 2020 Return-Path: Delivered-To: svn-src-stable-12@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id C952342BAC6; Mon, 5 Oct 2020 18:08:53 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4C4pWT4qvmz4Hwc; Mon, 5 Oct 2020 18:08:53 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 89519195F1; Mon, 5 Oct 2020 18:08:53 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 095I8r9p093101; Mon, 5 Oct 2020 18:08:53 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 095I8rXN093099; Mon, 5 Oct 2020 18:08:53 GMT (envelope-from dim@FreeBSD.org) Message-Id: <202010051808.095I8rXN093099@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Mon, 5 Oct 2020 18:08:53 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r366452 - in stable: 11/contrib/llvm-project/clang/lib/Basic/Targets 11/contrib/llvm-project/llvm/lib/Target/X86 12/contrib/llvm-project/clang/lib/Basic/Targets 12/contrib/llvm-project/... X-SVN-Group: stable-12 X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in stable: 11/contrib/llvm-project/clang/lib/Basic/Targets 11/contrib/llvm-project/llvm/lib/Target/X86 12/contrib/llvm-project/clang/lib/Basic/Targets 12/contrib/llvm-project/llvm/lib/Target/X86 X-SVN-Commit-Revision: 366452 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable-12@freebsd.org X-Mailman-Version: 2.1.33 Precedence: list List-Id: SVN commit messages for only the 12-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 Oct 2020 18:08:53 -0000 Author: dim Date: Mon Oct 5 18:08:52 2020 New Revision: 366452 URL: https://svnweb.freebsd.org/changeset/base/366452 Log: Merge commit 0fac1c191 from llvm git (by Craig Topper): [X86] Allow Yz inline assembly constraint to choose ymm0 or zmm0 when avx/avx512 are enabled and type is 256 or 512 bits gcc supports selecting ymm0/zmm0 for the Yz constraint when used with 256 or 512 bit vector types. Fixes PR45806 Differential Revision: https://reviews.llvm.org/D79448 This should fix 'fatal error: error in backend: Cannot select' errors if assertions are disabled, or 'Assertion failed: (isVector() && "Invalid vector type!"), function getVectorNumElements, file /usr/src/contrib/llvm-project/llvm/include/llvm/CodeGen/ValueTypes.h, line 276.', when building the audio/lsp-plugins-lv2 port. Direct commit to stable/{11,12} since head has clang 11.0.0, which already includes this fix. Reported by: yuri PR: 232911 Modified: stable/12/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp Changes in other areas also in this revision: Modified: stable/11/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp stable/11/contrib/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp Modified: stable/12/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp ============================================================================== --- stable/12/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp Mon Oct 5 16:39:38 2020 (r366451) +++ stable/12/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp Mon Oct 5 18:08:52 2020 (r366452) @@ -1772,8 +1772,14 @@ bool X86TargetInfo::validateOperandSize(const llvm::St return Size <= 64; case 'z': case '0': - // XMM0 - if (FeatureMap.lookup("sse")) + // XMM0/YMM/ZMM0 + if (FeatureMap.lookup("avx512f")) + // ZMM0 can be used if target supports AVX512F. + return Size <= 512U; + else if (FeatureMap.lookup("avx")) + // YMM0 can be used if target supports AVX. + return Size <= 256U; + else if (FeatureMap.lookup("sse")) return Size <= 128U; return false; case 'i': Modified: stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp ============================================================================== --- stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp Mon Oct 5 16:39:38 2020 (r366451) +++ stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp Mon Oct 5 18:08:52 2020 (r366452) @@ -46555,7 +46555,9 @@ TargetLowering::ConstraintWeight // XMM0 case 'z': case '0': - if ((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1()) + if (((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1()) || + ((type->getPrimitiveSizeInBits() == 256) && Subtarget.hasAVX()) || + ((type->getPrimitiveSizeInBits() == 512) && Subtarget.hasAVX512())) return CW_SpecificReg; return CW_Invalid; // Conditional OpMask regs (AVX512) @@ -47005,6 +47007,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const if (Subtarget.hasAVX()) return std::make_pair(0U, &X86::VR256RegClass); break; + case MVT::v64i8: + case MVT::v32i16: case MVT::v8f64: case MVT::v16f32: case MVT::v16i32: @@ -47030,7 +47034,42 @@ X86TargetLowering::getRegForInlineAsmConstraint(const case 'z': case '0': if (!Subtarget.hasSSE1()) break; - return std::make_pair(X86::XMM0, &X86::VR128RegClass); + switch (VT.SimpleTy) { + default: break; + // Scalar SSE types. + case MVT::f32: + case MVT::i32: + return std::make_pair(X86::XMM0, &X86::FR32RegClass); + case MVT::f64: + case MVT::i64: + return std::make_pair(X86::XMM0, &X86::FR64RegClass); + case MVT::f128: + case MVT::v16i8: + case MVT::v8i16: + case MVT::v4i32: + case MVT::v2i64: + case MVT::v4f32: + case MVT::v2f64: + return std::make_pair(X86::XMM0, &X86::VR128RegClass); + // AVX types. + case MVT::v32i8: + case MVT::v16i16: + case MVT::v8i32: + case MVT::v4i64: + case MVT::v8f32: + case MVT::v4f64: + if (Subtarget.hasAVX()) + return std::make_pair(X86::YMM0, &X86::VR256RegClass); + break; + case MVT::v8f64: + case MVT::v16f32: + case MVT::v16i32: + case MVT::v8i64: + if (Subtarget.hasAVX512()) + return std::make_pair(X86::ZMM0, &X86::VR512_0_15RegClass); + break; + } + break; case 'k': // This register class doesn't allocate k0 for masked vector operation. if (Subtarget.hasAVX512()) {