Date: Tue, 27 Nov 2018 17:02:15 +0000 (UTC) From: Mark Johnston <markj@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r341080 - stable/12/sys/riscv/include Message-ID: <201811271702.wARH2Flk050884@repo.freebsd.org>
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Author: markj Date: Tue Nov 27 17:02:15 2018 New Revision: 341080 URL: https://svnweb.freebsd.org/changeset/base/341080 Log: MFC r340399: RISC-V: Add macros for reading performance counter CSRs. Modified: stable/12/sys/riscv/include/cpufunc.h stable/12/sys/riscv/include/riscvreg.h Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/riscv/include/cpufunc.h ============================================================================== --- stable/12/sys/riscv/include/cpufunc.h Tue Nov 27 17:00:47 2018 (r341079) +++ stable/12/sys/riscv/include/cpufunc.h Tue Nov 27 17:02:15 2018 (r341080) @@ -104,6 +104,11 @@ sfence_vma_page(uintptr_t addr) __asm __volatile("sfence.vma %0" :: "r" (addr) : "memory"); } +#define rdcycle() csr_read64(cycle) +#define rdtime() csr_read64(time) +#define rdinstret() csr_read64(instret) +#define rdhpmcounter(n) csr_read64(hpmcounter##n) + #define cpufunc_nullop() riscv_nullop() void riscv_nullop(void); Modified: stable/12/sys/riscv/include/riscvreg.h ============================================================================== --- stable/12/sys/riscv/include/riscvreg.h Tue Nov 27 17:00:47 2018 (r341079) +++ stable/12/sys/riscv/include/riscvreg.h Tue Nov 27 17:02:15 2018 (r341080) @@ -223,4 +223,23 @@ val; \ }) +#if __riscv_xlen == 32 +#define csr_read64(csr) \ +({ uint64_t val; \ + uint32_t high, low; \ + __asm __volatile("1: " \ + "csrr t0, " #csr "h\n" \ + "csrr %0, " #csr "\n" \ + "csrr %1, " #csr "h\n" \ + "bne t0, %1, 1b" \ + : "=r" (low), "=r" (high) \ + : \ + : "t0"); \ + val = (low | ((uint64_t)high << 32)); \ + val; \ +}) +#else +#define csr_read64(csr) ((uint64_t)csr_read(csr)) +#endif + #endif /* !_MACHINE_RISCVREG_H_ */
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