Date: Tue, 26 Feb 2008 15:22:55 GMT From: "Randall R. Stewart" <rrs@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 136260 for review Message-ID: <200802261522.m1QFMtIV050018@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=136260 Change 136260 by rrs@rrs-mips2-jnpr on 2008/02/26 15:22:00 Puts the enable in the right place. Still not sure why the ei/di instruction blows up in the assembly and I have to use .word Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/psraccess.S#6 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/psraccess.S#6 (text+ko) ==== @@ -119,11 +119,24 @@ */ LEAF(enableintr) +#ifdef TARGET_OCTEON + .set mips64 + .word 0x041626020 #ei v0 + and v0, SR_INT_ENAB # return old interrupt enable bit +#if defined(ISA_MIPS32) + .set mips32 +#elif defined(ISA_MIPS64) + .set mips64 +#elif defined(ISA_MIPS3) + .set mips3 +#endif +#else mfc0 v0, COP_0_STATUS_REG # read status register nop or v1, v0, SR_INT_ENAB mtc0 v1, COP_0_STATUS_REG # enable all interrupts and v0, SR_INT_ENAB # return old interrupt enable +#endif j ra nop END(enableintr) @@ -155,18 +168,6 @@ END(disableintr) LEAF(set_intr_mask) -#ifdef TARGET_OCTEON - .set mips64 - .word 0x041626020 #ei v0 - and v0, SR_INT_ENAB # return old interrupt enable bit -#if defined(ISA_MIPS32) - .set mips32 -#elif defined(ISA_MIPS64) - .set mips64 -#elif defined(ISA_MIPS3) - .set mips3 -#endif -#else li t0, SR_INT_MASK # 1 means masked so invert. not a0, a0 # 1 means masked so invert. and a0, t0 # 1 means masked so invert. @@ -177,7 +178,6 @@ mtc0 v1, COP_0_STATUS_REG MIPS_CPU_NOP_DELAY move v0, v1 -#endif jr ra nop
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