From owner-svn-src-head@freebsd.org Thu Nov 17 14:41:24 2016 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 31011C47DAA; Thu, 17 Nov 2016 14:41:24 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 0B534BEE; Thu, 17 Nov 2016 14:41:23 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id uAHEfNkL060157; Thu, 17 Nov 2016 14:41:23 GMT (envelope-from br@FreeBSD.org) Received: (from br@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id uAHEfN8W060154; Thu, 17 Nov 2016 14:41:23 GMT (envelope-from br@FreeBSD.org) Message-Id: <201611171441.uAHEfN8W060154@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: br set sender to br@FreeBSD.org using -f From: Ruslan Bukin Date: Thu, 17 Nov 2016 14:41:23 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r308750 - in head/sys/dev: ic uart X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Nov 2016 14:41:24 -0000 Author: br Date: Thu Nov 17 14:41:22 2016 New Revision: 308750 URL: https://svnweb.freebsd.org/changeset/base/308750 Log: Add support for UART found in the Ingenic XBurst system on chips. These CPUs has non-standard UART enable bit hidden in the UART FIFO Control Register. Sponsored by: DARPA, AFRL Modified: head/sys/dev/ic/ns16550.h head/sys/dev/uart/uart_dev_ns8250.c Modified: head/sys/dev/ic/ns16550.h ============================================================================== --- head/sys/dev/ic/ns16550.h Thu Nov 17 14:32:23 2016 (r308749) +++ head/sys/dev/ic/ns16550.h Thu Nov 17 14:41:22 2016 (r308750) @@ -156,6 +156,9 @@ #define FIFO_XMT_RST FCR_XMT_RST #define FCR_DMA 0x08 #define FIFO_DMA_MODE FCR_DMA +#ifdef CPU_XBURST +#define FCR_UART_ON 0x10 +#endif #define FCR_RX_LOW 0x00 #define FIFO_RX_LOW FCR_RX_LOW #define FCR_RX_MEDL 0x40 Modified: head/sys/dev/uart/uart_dev_ns8250.c ============================================================================== --- head/sys/dev/uart/uart_dev_ns8250.c Thu Nov 17 14:32:23 2016 (r308749) +++ head/sys/dev/uart/uart_dev_ns8250.c Thu Nov 17 14:41:22 2016 (r308750) @@ -198,6 +198,9 @@ ns8250_flush(struct uart_bas *bas, int w uint8_t fcr; fcr = FCR_ENABLE; +#ifdef CPU_XBURST + fcr |= FCR_UART_ON; +#endif if (what & UART_FLUSH_TRANSMITTER) fcr |= FCR_XMT_RST; if (what & UART_FLUSH_RECEIVER) @@ -268,6 +271,10 @@ ns8250_probe(struct uart_bas *bas) { u_char val; +#ifdef CPU_XBURST + uart_setreg(bas, REG_FCR, FCR_UART_ON); +#endif + /* Check known 0 bits that don't depend on DLAB. */ val = uart_getreg(bas, REG_IIR); if (val & 0x30) @@ -289,7 +296,7 @@ static void ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { - u_char ier; + u_char ier, val; if (bas->rclk == 0) bas->rclk = DEFAULT_RCLK; @@ -306,7 +313,11 @@ ns8250_init(struct uart_bas *bas, int ba uart_barrier(bas); /* Disable the FIFO (if present). */ - uart_setreg(bas, REG_FCR, 0); + val = 0; +#ifdef CPU_XBURST + val = FCR_UART_ON; +#endif + uart_setreg(bas, REG_FCR, val); uart_barrier(bas); /* Set RTS & DTR. */ @@ -461,6 +472,9 @@ ns8250_bus_attach(struct uart_softc *sc) ns8250->mcr = uart_getreg(bas, REG_MCR); ns8250->fcr = FCR_ENABLE; +#ifdef CPU_XBURST + ns8250->fcr |= FCR_UART_ON; +#endif if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", &ivar)) { if (UART_FLAGS_FCR_RX_LOW(ivar)) @@ -753,6 +767,7 @@ ns8250_bus_probe(struct uart_softc *sc) struct uart_bas *bas; int count, delay, error, limit; uint8_t lsr, mcr, ier; + uint8_t val; ns8250 = (struct ns8250_softc *)sc; bas = &sc->sc_bas; @@ -786,7 +801,11 @@ ns8250_bus_probe(struct uart_softc *sc) * done. Since this is the first time we enable the FIFOs, we reset * them. */ - uart_setreg(bas, REG_FCR, FCR_ENABLE); + val = FCR_ENABLE; +#ifdef CPU_XBURST + val |= FCR_UART_ON; +#endif + uart_setreg(bas, REG_FCR, val); uart_barrier(bas); if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { /* @@ -800,7 +819,11 @@ ns8250_bus_probe(struct uart_softc *sc) return (0); } - uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); + val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST; +#ifdef CPU_XBURST + val |= FCR_UART_ON; +#endif + uart_setreg(bas, REG_FCR, val); uart_barrier(bas); count = 0; @@ -810,7 +833,11 @@ ns8250_bus_probe(struct uart_softc *sc) error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); if (error) { uart_setreg(bas, REG_MCR, mcr); - uart_setreg(bas, REG_FCR, 0); + val = 0; +#ifdef CPU_XBURST + val |= FCR_UART_ON; +#endif + uart_setreg(bas, REG_FCR, val); uart_barrier(bas); goto describe; } @@ -840,7 +867,11 @@ ns8250_bus_probe(struct uart_softc *sc) ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; uart_setreg(bas, REG_IER, ier); uart_setreg(bas, REG_MCR, mcr); - uart_setreg(bas, REG_FCR, 0); + val = 0; +#ifdef CPU_XBURST + val |= FCR_UART_ON; +#endif + uart_setreg(bas, REG_FCR, val); uart_barrier(bas); count = 0; goto describe;