From owner-cvs-all@FreeBSD.ORG Wed Sep 10 18:06:20 2008 Return-Path: Delivered-To: cvs-all@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id DD33B1065742; Wed, 10 Sep 2008 18:06:20 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id C7B188FC12; Wed, 10 Sep 2008 18:06:20 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id m8AI6KwT097092; Wed, 10 Sep 2008 18:06:20 GMT (envelope-from jhb@repoman.freebsd.org) Received: (from svn2cvs@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id m8AI6KOH097091; Wed, 10 Sep 2008 18:06:20 GMT (envelope-from jhb@repoman.freebsd.org) Message-Id: <200809101806.m8AI6KOH097091@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: svn2cvs set sender to jhb@repoman.freebsd.org using -f From: John Baldwin Date: Wed, 10 Sep 2008 18:06:08 +0000 (UTC) To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org X-FreeBSD-CVS-Branch: HEAD Cc: Subject: cvs commit: src/sys/amd64/pci pci_cfgreg.c src/sys/i386/pci pci_cfgreg.c X-BeenThere: cvs-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: CVS commit messages for the entire tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Sep 2008 18:06:21 -0000 jhb 2008-09-10 18:06:08 UTC FreeBSD src repository Modified files: sys/amd64/pci pci_cfgreg.c sys/i386/pci pci_cfgreg.c Log: SVN rev 182910 on 2008-09-10 18:06:08Z by jhb Some K8 chipsets don't expose all of the PCI devices on bus 0 via PCIe memory-mapped config access. Add a workaround for these systems by checking the first function of each slot on bus 0 using both the memory-mapped config access and the older type 1 I/O port config access. If we find a slot that is only visible via the type 1 I/O port config access, we flag that slot. Future PCI config transactions to flagged slots on bus 0 use type 1 I/O port config access rather than memory mapped config access. Revision Changes Path 1.112 +48 -14 src/sys/amd64/pci/pci_cfgreg.c 1.131 +44 -14 src/sys/i386/pci/pci_cfgreg.c