From owner-freebsd-amd64@FreeBSD.ORG Wed Jun 2 17:19:17 2004 Return-Path: Delivered-To: freebsd-amd64@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 02C7C16A4CE; Wed, 2 Jun 2004 17:19:17 -0700 (PDT) Received: from smtp01.syd.iprimus.net.au (smtp01.syd.iprimus.net.au [210.50.30.52]) by mx1.FreeBSD.org (Postfix) with ESMTP id 478A643D48; Wed, 2 Jun 2004 17:19:16 -0700 (PDT) (envelope-from tim@robbins.dropbear.id.au) Received: from robbins.dropbear.id.au (210.50.200.168) by smtp01.syd.iprimus.net.au (7.0.024) id 40B7A0DA00186C44; Thu, 3 Jun 2004 10:19:14 +1000 Received: by robbins.dropbear.id.au (Postfix, from userid 1000) id 13F0741CB; Thu, 3 Jun 2004 10:20:15 +1000 (EST) Date: Thu, 3 Jun 2004 10:20:15 +1000 From: Tim Robbins To: David Schultz Message-ID: <20040603002015.GA14544@cat.robbins.dropbear.id.au> References: <20040602064846.GA6124@VARK.homeunix.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20040602064846.GA6124@VARK.homeunix.com> User-Agent: Mutt/1.4.1i cc: amd64@freebsd.org Subject: Re: Initial FP exception flags incorrect on amd64 X-BeenThere: freebsd-amd64@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Porting FreeBSD to the AMD64 platform List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Jun 2004 00:19:17 -0000 On Tue, Jun 01, 2004 at 11:48:46PM -0700, David Schultz wrote: > I discovered that new processes on amd64 have the inexact flag > raised by default, at least on sledge. However, all the sticky > flags should be clear initially. [...] > I don't have any amd64 hardware of my own to test kernel patches > on, but if I were to make a wild guess as to how to solve the > problem, it would be the following patch. I would appreciate it > if someone could address the problem, or at least let me know > whether my proposed fix works. > > Index: sys/amd64/amd64/fpu.c > =================================================================== > RCS file: /cvs/src/sys/amd64/amd64/fpu.c,v > retrieving revision 1.149 > diff -u -r1.149 fpu.c > --- fpu.c 5 Apr 2004 21:25:51 -0000 1.149 > +++ fpu.c 2 Jun 2004 06:08:34 -0000 > @@ -73,6 +73,7 @@ > #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) > #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) > #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) > +#define stmxcsr(addr) __asm("stmxcsr %0" : "=m" (*(addr))) > #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ > : : "n" (CR0_TS) : "ax") > #define stop_emulating() __asm("clts") > @@ -119,6 +120,8 @@ > fninit(); > control = __INITIAL_FPUCW__; > fldcw(&control); > + control = __INITIAL_MXCSR__; > + stmxcsr(&control); > fxsave(&fpu_cleanstate); > start_emulating(); > fpu_cleanstate_ready = 1; This seems to cause a panic (trap 12) on startup. Shouldn't it be ldmxcsr instead? Changing that causes a different kind of panic (trap 9.) Tim