From owner-freebsd-hackers Fri Apr 7 15:56:09 1995 Return-Path: hackers-owner Received: (from majordom@localhost) by freefall.cdrom.com (8.6.10/8.6.6) id PAA22649 for hackers-outgoing; Fri, 7 Apr 1995 15:56:09 -0700 Received: from lyria.stanford.edu (lyria.Stanford.EDU [36.146.0.57]) by freefall.cdrom.com (8.6.10/8.6.6) with ESMTP id PAA22642 for ; Fri, 7 Apr 1995 15:56:08 -0700 Received: (from teren@localhost) by lyria.stanford.edu (8.6.11/8.6.9) id QAA25163; Fri, 7 Apr 1995 16:04:02 -0700 Date: Fri, 7 Apr 1995 16:04:01 -0700 (PDT) From: Terry Lee To: Soeren Schmidt cc: FreeBSD hackers Subject: Re: Intel 486"Enhanced Write Back" question In-Reply-To: <199504061849.AA09676@dkuug.dk> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: hackers-owner@FreeBSD.org Precedence: bulk > I have these new 486 "enhanced writeback" CPU's lying around, but > I cannot use the WB feature. I've read that the CPU determines if > it shall work as a WB or WT chip by reading the level on some pin > on reset. This makes sense as old motherboard designs wouldn't > support this feature then. Now the question is which pin ?? B13 must be high. A10, A12, and B12 are also used to control cache flushes and the like. Looks like your motherboard needs to support it specifically. This is from the 486 databook which Intel will send you for free if you give them a call. Interesting that AMD uses B13 in their DX4 to specify clock triple or clock double mode. I N T E R N E T Terry Lee, Technical Director D E S I G N 745 Stanford Avenue, Palo Alto, California 94306 G R O U P 415 424 0747 voice 415 424-0751 fax http://www.mall.net terryl@cs.stanford.edu http://www.mall.net/terry