From owner-freebsd-smp Sun Mar 31 10:17:20 2002 Delivered-To: freebsd-smp@freebsd.org Received: from wall.polstra.com (wall-gw.polstra.com [206.213.73.130]) by hub.freebsd.org (Postfix) with ESMTP id E73DA37B41C for ; Sun, 31 Mar 2002 10:17:15 -0800 (PST) Received: from vashon.polstra.com (vashon.polstra.com [206.213.73.13]) by wall.polstra.com (8.11.3/8.11.3) with ESMTP id g2VIHEo96427; Sun, 31 Mar 2002 10:17:14 -0800 (PST) (envelope-from jdp@wall.polstra.com) Received: (from jdp@localhost) by vashon.polstra.com (8.11.6/8.11.0) id g2VIHEB18544; Sun, 31 Mar 2002 10:17:14 -0800 (PST) (envelope-from jdp) Date: Sun, 31 Mar 2002 10:17:14 -0800 (PST) Message-Id: <200203311817.g2VIHEB18544@vashon.polstra.com> To: smp@freebsd.org From: John Polstra Cc: dillon@apollo.backplane.com Subject: Re: RE: Syscall contention tests return, userret() bugs/issues. In-Reply-To: <200203311809.g2VI90H89605@apollo.backplane.com> References: <200203311747.g2VHlII89488@apollo.backplane.com> <200203311752.g2VHqab18408@vashon.polstra.com> <200203311809.g2VI90H89605@apollo.backplane.com> Organization: Polstra & Co., Seattle, WA Sender: owner-freebsd-smp@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.org In article <200203311809.g2VI90H89605@apollo.backplane.com>, Matthew Dillon wrote: > : > :Why do you keep saying the Intel caches are write-through? They've > :been write-back since the Pentium. See table 9-2 in the same document > :I cited before. > : > Maybe I'm using the wrong terminology. What I mean to say is that > Intel caches, under most conditions, will flush dirty elements in > their caches to main memory very quickly. i.e. unlike, say, the old > 68040 cache which leaves dirty cache lines in the cache almost > indefinitely. The intel caches implement a write ordering constraint > and a FIFO to deal with dirty data. > > Yes, I guess that would be write-back rather then write-through, > But not delayed-write. It is both write-back and delayed-write. Section 9.10 ("Store Buffer") describes it: IA-32 processors temporarily store each write (store) to memory in a store buffer. The store buffer improves processor performance by allowing the processor to continue executing instructions without having to wait until a write to memory and/or to a cache is complete. It also allows writes to be delayed for more efficient use of memory-access bus cycles. Table 9-1 states that the store buffer has 24 entries on the Pentium 4, and 12 entries on the P6 family. John -- John Polstra John D. Polstra & Co., Inc. Seattle, Washington USA "Disappointment is a good sign of basic intelligence." -- Chögyam Trungpa To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-smp" in the body of the message