Date: Sat, 17 Mar 2012 07:25:24 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r233081 - head/sys/mips/atheros Message-ID: <201203170725.q2H7POxr056085@svn.freebsd.org>
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Author: adrian Date: Sat Mar 17 07:25:23 2012 New Revision: 233081 URL: http://svn.freebsd.org/changeset/base/233081 Log: Begin fleshing out MII clock rate configuration changes. These are needed for some particular port configurations where the default speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit PLL rate requires a similar MII clock rate, rather than a fixed MII rate.) This is: * only currently implemented for the ar71xx; * isn't used anywhere (yet), as the final interface for this hasn't yet been determined. Modified: head/sys/mips/atheros/ar71xx_chip.c head/sys/mips/atheros/ar71xx_cpudef.h head/sys/mips/atheros/ar71xxreg.h head/sys/mips/atheros/ar724x_chip.c head/sys/mips/atheros/ar91xx_chip.c Modified: head/sys/mips/atheros/ar71xx_chip.c ============================================================================== --- head/sys/mips/atheros/ar71xx_chip.c Sat Mar 17 06:54:42 2012 (r233080) +++ head/sys/mips/atheros/ar71xx_chip.c Sat Mar 17 07:25:23 2012 (r233081) @@ -136,6 +136,46 @@ ar71xx_chip_device_stopped(uint32_t mask return ((reg & mask) == mask); } +static void +ar71xx_chip_set_mii_speed(uint32_t unit, uint32_t speed) +{ + uint32_t val, reg, ctrl; + + switch (unit) { + case 0: + reg = AR71XX_MII0_CTRL; + break; + case 1: + reg = AR71XX_MII1_CTRL; + break; + default: + printf("%s: invalid MII unit set for arge unit: %d\n", + __func__, unit); + return; + } + + switch (speed) { + case 10: + ctrl = MII_CTRL_SPEED_10; + break; + case 100: + ctrl = MII_CTRL_SPEED_100; + break; + case 1000: + ctrl = MII_CTRL_SPEED_1000; + break; + default: + printf("%s: invalid MII speed (%d) set for arge unit: %d\n", + __func__, speed, unit); + return; + } + + val = ATH_READ_REG(reg); + val &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT); + val |= (ctrl & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT; + ATH_WRITE_REG(reg, val); +} + /* Speed is either 10, 100 or 1000 */ static void ar71xx_chip_set_pll_ge(int unit, int speed) @@ -237,6 +277,7 @@ struct ar71xx_cpu_def ar71xx_chip_def = &ar71xx_chip_device_start, &ar71xx_chip_device_stopped, &ar71xx_chip_set_pll_ge, + &ar71xx_chip_set_mii_speed, &ar71xx_chip_ddr_flush_ge, &ar71xx_chip_get_eth_pll, &ar71xx_chip_ddr_flush_ip2, Modified: head/sys/mips/atheros/ar71xx_cpudef.h ============================================================================== --- head/sys/mips/atheros/ar71xx_cpudef.h Sat Mar 17 06:54:42 2012 (r233080) +++ head/sys/mips/atheros/ar71xx_cpudef.h Sat Mar 17 07:25:23 2012 (r233081) @@ -36,6 +36,7 @@ struct ar71xx_cpu_def { void (* ar71xx_chip_device_start) (uint32_t); int (* ar71xx_chip_device_stopped) (uint32_t); void (* ar71xx_chip_set_pll_ge) (int, int); + void (* ar71xx_chip_set_mii_speed) (uint32_t, uint32_t); void (* ar71xx_chip_ddr_flush_ge) (int); uint32_t (* ar71xx_chip_get_eth_pll) (unsigned int, int); @@ -84,6 +85,11 @@ static inline void ar71xx_device_set_pll ar71xx_cpu_ops->ar71xx_chip_set_pll_ge(unit, speed); } +static inline void ar71xx_device_set_mii_speed(int unit, int speed) +{ + ar71xx_cpu_ops->ar71xx_chip_set_mii_speed(unit, speed); +} + static inline void ar71xx_device_flush_ddr_ge(int unit) { ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ge(unit); Modified: head/sys/mips/atheros/ar71xxreg.h ============================================================================== --- head/sys/mips/atheros/ar71xxreg.h Sat Mar 17 06:54:42 2012 (r233080) +++ head/sys/mips/atheros/ar71xxreg.h Sat Mar 17 07:25:23 2012 (r233081) @@ -268,6 +268,17 @@ #define AR91XX_REV_ID_REVISION_SHIFT 2 /* + * AR71xx MII control region + */ +#define AR71XX_MII0_CTRL 0x18070000 +#define AR71XX_MII1_CTRL 0x18070004 +#define MII_CTRL_SPEED_SHIFT 4 +#define MII_CTRL_SPEED_MASK 3 +#define MII_CTRL_SPEED_10 0 +#define MII_CTRL_SPEED_100 1 +#define MII_CTRL_SPEED_1000 2 + +/* * GigE adapters region */ #define AR71XX_MAC0_BASE 0x19000000 Modified: head/sys/mips/atheros/ar724x_chip.c ============================================================================== --- head/sys/mips/atheros/ar724x_chip.c Sat Mar 17 06:54:42 2012 (r233080) +++ head/sys/mips/atheros/ar724x_chip.c Sat Mar 17 07:25:23 2012 (r233081) @@ -123,6 +123,13 @@ ar724x_chip_device_stopped(uint32_t mask } static void +ar724x_chip_set_mii_speed(uint32_t unit, uint32_t speed) +{ + /* XXX TODO */ + return; +} + +static void ar724x_chip_set_pll_ge(int unit, int speed) { @@ -220,6 +227,7 @@ struct ar71xx_cpu_def ar724x_chip_def = &ar724x_chip_device_start, &ar724x_chip_device_stopped, &ar724x_chip_set_pll_ge, + &ar724x_chip_set_mii_speed, &ar724x_chip_ddr_flush_ge, &ar724x_chip_get_eth_pll, &ar724x_chip_ddr_flush_ip2, Modified: head/sys/mips/atheros/ar91xx_chip.c ============================================================================== --- head/sys/mips/atheros/ar91xx_chip.c Sat Mar 17 06:54:42 2012 (r233080) +++ head/sys/mips/atheros/ar91xx_chip.c Sat Mar 17 07:25:23 2012 (r233081) @@ -111,6 +111,13 @@ ar91xx_chip_device_stopped(uint32_t mask } static void +ar91xx_chip_set_mii_speed(uint32_t unit, uint32_t speed) +{ + /* XXX TODO */ +} + + +static void ar91xx_chip_set_pll_ge(int unit, int speed) { uint32_t pll; @@ -209,6 +216,7 @@ struct ar71xx_cpu_def ar91xx_chip_def = &ar91xx_chip_device_start, &ar91xx_chip_device_stopped, &ar91xx_chip_set_pll_ge, + &ar91xx_chip_set_mii_speed, &ar91xx_chip_ddr_flush_ge, &ar91xx_chip_get_eth_pll, &ar91xx_chip_ddr_flush_ip2,
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