Date: Mon, 9 Sep 1996 08:23:02 -0500 (CDT) From: Chris Csanady <ccsanady@friley216.res.iastate.edu> To: freebsd-questions@FreeBSD.ORG Subject: Intel SMP cache architecture question.. Message-ID: <199609091323.IAA19237@friley216.res.iastate.edu>
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I am planning on buying a dual proccessor pentium, and I was just curious as to the way the caching is done. I recently noticed the lmbench summary on this list that has the XXpress as having 2 seperate caches, while all others Ive seen have a single cache. So on the single cache boards.. are they split logically? Well, I dont have too much money, so I'll probably end up going with the Tyan tomcat II.. unless someone would like to point out that it doesnt work at all. ;) Laters, chris
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