Date: Wed, 16 Jul 1997 17:49:00 -0600 From: Steve Passe <smp@csn.net> To: Kevin Van Maren <vanmaren@marker.cs.utah.edu> Cc: smp@FreeBSD.ORG Subject: Re: mptable from DELL 4100 Message-ID: <199707162349.RAA10695@Ilsa.StevesCafe.com> In-Reply-To: Your message of "Wed, 16 Jul 1997 17:22:29 MDT." <199707162322.RAA09970@marker.cs.utah.edu>
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Hi, > I tried to add a second CPU, but the stepping wasn't `new enough' to > make the BIOS happy. I don't have the machine anymore, but this is > what it looked like with 1 processor. Maybe someone has annother > DELL server with multiple processors? > ... If this is related to the current discussion of EISA hardware, this motherboard should have no problem as it (claims*) to have the timer attached directly to the IO APIC: > I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID INT# > ... > INT conforms conforms 2 0 1 2 more specifically since the 8254 is attached to the IO APIC, the 8259 could be used to pass the EISA DMA chaining INTs to the APIC IF someone cared enough to write the code... --- *PS: I'm working on a theory that those systems that currently require "options SMP_TIMER_NC" don't really, but that its an issue of additional programming of the MB chipset. -- Steve Passe | powered by smp@csn.net | Symmetric MultiProcessor FreeBSD
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