Date: Tue, 13 Nov 2012 14:01:07 +0000 (UTC) From: Aleksandr Rybalko <ray@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r242963 - projects/efika_mx/sys/dev/uart Message-ID: <201211131401.qADE17RZ057349@svn.freebsd.org>
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Author: ray Date: Tue Nov 13 14:01:07 2012 New Revision: 242963 URL: http://svnweb.freebsd.org/changeset/base/242963 Log: Now we have good UART console for i.MX5xx. Added: projects/efika_mx/sys/dev/uart/uart_dev_imx.c projects/efika_mx/sys/dev/uart/uart_dev_imx5xx.h Added: projects/efika_mx/sys/dev/uart/uart_dev_imx.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/efika_mx/sys/dev/uart/uart_dev_imx.c Tue Nov 13 14:01:07 2012 (r242963) @@ -0,0 +1,435 @@ +/*- + * Copyright (c) 2012 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Oleksandr Rybalko under sponsorship + * from the FreeBSD Foundation. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include "opt_ddb.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/conf.h> +#include <sys/kdb.h> +#include <machine/bus.h> +#include <machine/fdt.h> + +#include <dev/uart/uart.h> +#include <dev/uart/uart_cpu.h> +#include <dev/uart/uart_bus.h> + +#include <dev/uart/uart_dev_imx5xx.h> + +#include "uart_if.h" +/* + * Low-level UART interface. + */ +static int imx_uart_probe(struct uart_bas *bas); +static void imx_uart_init(struct uart_bas *bas, int, int, int, int); +static void imx_uart_term(struct uart_bas *bas); +static void imx_uart_putc(struct uart_bas *bas, int); +static int imx_uart_rxready(struct uart_bas *bas); +static int imx_uart_getc(struct uart_bas *bas, struct mtx *); + +static struct uart_ops uart_imx_uart_ops = { + .probe = imx_uart_probe, + .init = imx_uart_init, + .term = imx_uart_term, + .putc = imx_uart_putc, + .rxready = imx_uart_rxready, + .getc = imx_uart_getc, +}; + +static int +imx_uart_probe(struct uart_bas *bas) +{ + + return (0); +} + +static void +imx_uart_init(struct uart_bas *bas, int baudrate, int databits, + int stopbits, int parity) +{ + +} + +static void +imx_uart_term(struct uart_bas *bas) +{ + +} + +static void +imx_uart_putc(struct uart_bas *bas, int c) +{ + + while (!(IS(bas, USR2, TXFE))) + ; + SETREG(bas, REG(UTXD), c); +} + +static int +imx_uart_rxready(struct uart_bas *bas) +{ + + return ((IS(bas, USR2, RDR)) ? 1 : 0); +} + +static int +imx_uart_getc(struct uart_bas *bas, struct mtx *hwmtx) +{ + int c; + + uart_lock(hwmtx); + while (!(IS(bas, USR2, RDR))) + ; + + c = GETREG(bas, REG(URXD)); + uart_unlock(hwmtx); +#if defined(KDB) + if (c & FLD(URXD, BRK)) { + if (kdb_break()) + return (0); + } +#endif + return (c & 0xff); +} + +/* + * High-level UART interface. + */ +struct imx_uart_softc { + struct uart_softc base; +}; + +static int imx_uart_bus_attach(struct uart_softc *); +static int imx_uart_bus_detach(struct uart_softc *); +static int imx_uart_bus_flush(struct uart_softc *, int); +static int imx_uart_bus_getsig(struct uart_softc *); +static int imx_uart_bus_ioctl(struct uart_softc *, int, intptr_t); +static int imx_uart_bus_ipend(struct uart_softc *); +static int imx_uart_bus_param(struct uart_softc *, int, int, int, int); +static int imx_uart_bus_probe(struct uart_softc *); +static int imx_uart_bus_receive(struct uart_softc *); +static int imx_uart_bus_setsig(struct uart_softc *, int); +static int imx_uart_bus_transmit(struct uart_softc *); + +static kobj_method_t imx_uart_methods[] = { + KOBJMETHOD(uart_attach, imx_uart_bus_attach), + KOBJMETHOD(uart_detach, imx_uart_bus_detach), + KOBJMETHOD(uart_flush, imx_uart_bus_flush), + KOBJMETHOD(uart_getsig, imx_uart_bus_getsig), + KOBJMETHOD(uart_ioctl, imx_uart_bus_ioctl), + KOBJMETHOD(uart_ipend, imx_uart_bus_ipend), + KOBJMETHOD(uart_param, imx_uart_bus_param), + KOBJMETHOD(uart_probe, imx_uart_bus_probe), + KOBJMETHOD(uart_receive, imx_uart_bus_receive), + KOBJMETHOD(uart_setsig, imx_uart_bus_setsig), + KOBJMETHOD(uart_transmit, imx_uart_bus_transmit), + { 0, 0 } +}; + +struct uart_class uart_imx_class = { + "imx", + imx_uart_methods, + sizeof(struct imx_uart_softc), + .uc_ops = &uart_imx_uart_ops, + .uc_range = 0x100, + .uc_rclk = 24000000 /* TODO: get value from CCM */ +}; + +#define SIGCHG(c, i, s, d) \ + if (c) { \ + i |= (i & s) ? s : s | d; \ + } else { \ + i = (i & s) ? (i & ~s) | d : i; \ + } + +static int +imx_uart_bus_attach(struct uart_softc *sc) +{ + struct uart_bas *bas; + struct uart_devinfo *di; + + bas = &sc->sc_bas; + if (sc->sc_sysdev != NULL) { + di = sc->sc_sysdev; + imx_uart_init(bas, di->baudrate, di->databits, di->stopbits, + di->parity); + } else { + imx_uart_init(bas, 115200, 8, 1, 0); + } + + sc->sc_rxfifosz = 1; + sc->sc_txfifosz = 1; + + (void)imx_uart_bus_getsig(sc); + + /* XXX workaround to have working console on manut prompt */ + if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE){ + DIS(bas, UCR4, DREN); + } else { + ENA(bas, UCR4, DREN); + } + DIS(bas, UCR1, RRDYEN); + DIS(bas, UCR1, IDEN); + DIS(bas, UCR3, RXDSEN); + DIS(bas, UCR2, ATEN); + DIS(bas, UCR1, TXMPTYEN); + DIS(bas, UCR1, TRDYEN); + DIS(bas, UCR4, TCEN); + DIS(bas, UCR4, OREN); + ENA(bas, UCR4, BKEN); + DIS(bas, UCR4, WKEN); + DIS(bas, UCR1, ADEN); + DIS(bas, UCR3, ACIEN); + DIS(bas, UCR2, ESCI); + DIS(bas, UCR4, ENIRI); + DIS(bas, UCR3, AIRINTEN); + DIS(bas, UCR3, AWAKEN); + DIS(bas, UCR3, FRAERREN); + DIS(bas, UCR3, PARERREN); + DIS(bas, UCR1, RTSDEN); + DIS(bas, UCR2, RTSEN); + DIS(bas, UCR3, DTREN); + DIS(bas, UCR3, RI); + DIS(bas, UCR3, DCD); + DIS(bas, UCR3, DTRDEN); + + /* ACK all interrupts */ + SETREG(bas, REG(USR1), 0xffff); + SETREG(bas, REG(USR2), 0xffff); + return (0); +} + +static int +imx_uart_bus_detach(struct uart_softc *sc) +{ + + SETREG(&sc->sc_bas, REG(UCR4), 0); + + return (0); +} + +static int +imx_uart_bus_flush(struct uart_softc *sc, int what) +{ + + /* TODO */ + return (0); +} + +static int +imx_uart_bus_getsig(struct uart_softc *sc) +{ + uint32_t new, old, sig; + uint8_t bes; + + do { + old = sc->sc_hwsig; + sig = old; + uart_lock(sc->sc_hwmtx); + bes = GETREG(&sc->sc_bas, REG(USR2)); + uart_unlock(sc->sc_hwmtx); + /* XXX: chip can show delta */ + SIGCHG(bes & FLD(USR2, DCDIN), sig, SER_DCD, SER_DDCD); + new = sig & ~SER_MASK_DELTA; + } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); + + return (sig); +} + +static int +imx_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) +{ + struct uart_bas *bas; + int error; + + bas = &sc->sc_bas; + error = 0; + uart_lock(sc->sc_hwmtx); + switch (request) { + case UART_IOCTL_BREAK: + /* TODO */ + break; + case UART_IOCTL_BAUD: + /* TODO */ + *(int*)data = 115200; + break; + default: + error = EINVAL; + break; + } + uart_unlock(sc->sc_hwmtx); + + return (error); +} + +static int +imx_uart_bus_ipend(struct uart_softc *sc) +{ + struct uart_bas *bas; + int ipend; + uint32_t usr1, usr2; + uint32_t ucr1, ucr4; + + bas = &sc->sc_bas; + ipend = 0; + + uart_lock(sc->sc_hwmtx); + + /* Read pending interrupts */ + usr1 = GETREG(bas, REG(USR1)); + usr2 = GETREG(bas, REG(USR2)); + /* ACK interrupts */ + SETREG(bas, REG(USR1), usr1); + SETREG(bas, REG(USR2), usr2); + + ucr1 = GETREG(bas, REG(UCR1)); + ucr4 = GETREG(bas, REG(UCR4)); + + if ((usr2 & FLD(USR2, TXFE)) && (ucr1 & FLD(UCR1, TXMPTYEN))) { + DIS(bas, UCR1, TXMPTYEN); + /* Continue TXing */ + ipend |= SER_INT_TXIDLE; + } + if ((usr2 & FLD(USR2, RDR)) && (ucr4 & FLD(UCR4, DREN))) { + DIS(bas, UCR4, DREN); + /* Wow, new char on input */ + ipend |= SER_INT_RXREADY; + } + if ((usr2 & FLD(USR2, BRCD)) && (ucr4 & FLD(UCR4, BKEN))) + ipend |= SER_INT_BREAK; + + uart_unlock(sc->sc_hwmtx); + + return (ipend); +} + +static int +imx_uart_bus_param(struct uart_softc *sc, int baudrate, int databits, + int stopbits, int parity) +{ + + uart_lock(sc->sc_hwmtx); + imx_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity); + uart_unlock(sc->sc_hwmtx); + return (0); +} + +static int +imx_uart_bus_probe(struct uart_softc *sc) +{ + int error; + + error = imx_uart_probe(&sc->sc_bas); + if (error) + return (error); + + device_set_desc(sc->sc_dev, "imx_uart"); + return (0); +} + +static int +imx_uart_bus_receive(struct uart_softc *sc) +{ + struct uart_bas *bas; + int xc, out; + + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + + /* Read while we have anything in FIFO */ + while (IS(bas, USR2, RDR)) { + if (uart_rx_full(sc)) { + /* No space left in input buffer */ + sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; + break; + } + out = 0; + xc = GETREG(bas, REG(URXD)); + + /* We have valid char */ + if (xc & FLD(URXD, CHARRDY)) + out = xc & 0x000000ff; + + if (xc & FLD(URXD, FRMERR)) + out |= UART_STAT_FRAMERR; + if (xc & FLD(URXD, PRERR)) + out |= UART_STAT_PARERR; + if (xc & FLD(URXD, OVRRUN)) + out |= UART_STAT_OVERRUN; + if (xc & FLD(URXD, BRK)) + out |= UART_STAT_BREAK; + + uart_rx_put(sc, out); + } + /* Reenable Data Ready interrupt */ + ENA(bas, UCR4, DREN); + + uart_unlock(sc->sc_hwmtx); + return (0); +} + +static int +imx_uart_bus_setsig(struct uart_softc *sc, int sig) +{ + + /* TODO: implement (?) */ + + /* XXX workaround to have working console on manut prompt */ + /* Enable RX interrupt */ + if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) + if (!IS(&sc->sc_bas, UCR4, DREN)) + ENA(&sc->sc_bas, UCR4, DREN); + return (0); +} + +static int +imx_uart_bus_transmit(struct uart_softc *sc) +{ + struct uart_bas *bas = &sc->sc_bas; + int i; + + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + + /* Fill TX FIFO */ + for (i = 0; i < sc->sc_txdatasz; i++) { + SETREG(bas, REG(UTXD), sc->sc_txbuf[i] & 0xff); + } + + sc->sc_txbusy = 1; + /* Call me when ready */ + ENA(bas, UCR1, TXMPTYEN); + + uart_unlock(sc->sc_hwmtx); + + return (0); +} Added: projects/efika_mx/sys/dev/uart/uart_dev_imx5xx.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/efika_mx/sys/dev/uart/uart_dev_imx5xx.h Tue Nov 13 14:01:07 2012 (r242963) @@ -0,0 +1,221 @@ +/*- + * Copyright (c) 2012 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Oleksandr Rybalko under sponsorship + * from the FreeBSD Foundation. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _UART_DEV_IMX5XX_H +#define _UART_DEV_IMX5XX_H + +#define IMXUART_URXD_REG 0x0000 /* UART Receiver Register */ +#define IMXUART_URXD_CHARRDY (1 << 15) +#define IMXUART_URXD_ERR (1 << 14) +#define IMXUART_URXD_OVRRUN (1 << 13) +#define IMXUART_URXD_FRMERR (1 << 12) +#define IMXUART_URXD_BRK (1 << 11) +#define IMXUART_URXD_PRERR (1 << 10) +#define IMXUART_URXD_RX_DATA_MASK 0xff + +#define IMXUART_UTXD_REG 0x0040 /* UART Transmitter Register */ +#define IMXUART_UTXD_TX_DATA_MASK 0xff + +#define IMXUART_UCR1_REG 0x0080 /* UART Control Register 1 */ +#define IMXUART_UCR1_ADEN (1 << 15) +#define IMXUART_UCR1_ADBR (1 << 14) +#define IMXUART_UCR1_TRDYEN (1 << 13) +#define IMXUART_UCR1_IDEN (1 << 12) +#define IMXUART_UCR1_ICD_MASK (3 << 10) +#define IMXUART_UCR1_ICD_IDLE4 (0 << 10) +#define IMXUART_UCR1_ICD_IDLE8 (1 << 10) +#define IMXUART_UCR1_ICD_IDLE16 (2 << 10) +#define IMXUART_UCR1_ICD_IDLE32 (3 << 10) +#define IMXUART_UCR1_RRDYEN (1 << 9) +#define IMXUART_UCR1_RXDMAEN (1 << 8) +#define IMXUART_UCR1_IREN (1 << 7) +#define IMXUART_UCR1_TXMPTYEN (1 << 6) +#define IMXUART_UCR1_RTSDEN (1 << 5) +#define IMXUART_UCR1_SNDBRK (1 << 4) +#define IMXUART_UCR1_TXDMAEN (1 << 3) +#define IMXUART_UCR1_ATDMAEN (1 << 2) +#define IMXUART_UCR1_DOZE (1 << 1) +#define IMXUART_UCR1_UARTEN (1 << 0) + +#define IMXUART_UCR2_REG 0x0084 /* UART Control Register 2 */ +#define IMXUART_UCR2_ESCI (1 << 15) +#define IMXUART_UCR2_IRTS (1 << 14) +#define IMXUART_UCR2_CTSC (1 << 13) +#define IMXUART_UCR2_CTS (1 << 12) +#define IMXUART_UCR2_ESCEN (1 << 11) +#define IMXUART_UCR2_RTEC_MASK (3 << 9) +#define IMXUART_UCR2_RTEC_REDGE (0 << 9) +#define IMXUART_UCR2_RTEC_FEDGE (1 << 9) +#define IMXUART_UCR2_RTEC_EDGE (2 << 9) +#define IMXUART_UCR2_PREN (1 << 8) +#define IMXUART_UCR2_PROE (1 << 7) +#define IMXUART_UCR2_STPB (1 << 6) +#define IMXUART_UCR2_WS (1 << 5) +#define IMXUART_UCR2_RTSEN (1 << 4) +#define IMXUART_UCR2_ATEN (1 << 3) +#define IMXUART_UCR2_TXEN (1 << 2) +#define IMXUART_UCR2_RXEN (1 << 1) +#define IMXUART_UCR2_N_SRST (1 << 0) + +#define IMXUART_UCR3_REG 0x0088 /* UART Control Register 3 */ +#define IMXUART_UCR3_DPEC_MASK (3 << 14) +#define IMXUART_UCR3_DPEC_REDGE (0 << 14) +#define IMXUART_UCR3_DPEC_FEDGE (1 << 14) +#define IMXUART_UCR3_DPEC_EDGE (2 << 14) +#define IMXUART_UCR3_DTREN (1 << 13) +#define IMXUART_UCR3_PARERREN (1 << 12) +#define IMXUART_UCR3_FRAERREN (1 << 11) +#define IMXUART_UCR3_DSR (1 << 10) +#define IMXUART_UCR3_DCD (1 << 9) +#define IMXUART_UCR3_RI (1 << 8) +#define IMXUART_UCR3_ADNIMP (1 << 7) +#define IMXUART_UCR3_RXDSEN (1 << 6) +#define IMXUART_UCR3_AIRINTEN (1 << 5) +#define IMXUART_UCR3_AWAKEN (1 << 4) +#define IMXUART_UCR3_DTRDEN (1 << 3) +#define IMXUART_UCR3_RXDMUXSEL (1 << 2) +#define IMXUART_UCR3_INVT (1 << 1) +#define IMXUART_UCR3_ACIEN (1 << 0) + +#define IMXUART_UCR4_REG 0x008c /* UART Control Register 4 */ +#define IMXUART_UCR4_CTSTL_MASK (0x3f << 10) +#define IMXUART_UCR4_CTSTL_SHIFT 10 +#define IMXUART_UCR4_INVR (1 << 9) +#define IMXUART_UCR4_ENIRI (1 << 8) +#define IMXUART_UCR4_WKEN (1 << 7) +#define IMXUART_UCR4_IDDMAEN (1 << 6) +#define IMXUART_UCR4_IRSC (1 << 5) +#define IMXUART_UCR4_LPBYP (1 << 4) +#define IMXUART_UCR4_TCEN (1 << 3) +#define IMXUART_UCR4_BKEN (1 << 2) +#define IMXUART_UCR4_OREN (1 << 1) +#define IMXUART_UCR4_DREN (1 << 0) + +#define IMXUART_UFCR_REG 0x0090 /* UART FIFO Control Register */ +#define IMXUART_UFCR_TXTL_MASK (0x3f << 10) +#define IMXUART_UFCR_TXTL_SHIFT 10 +#define IMXUART_UFCR_RFDIV_MASK (0x07 << 7) +#define IMXUART_UFCR_RFDIV_SHIFT 7 +#define IMXUART_UFCR_RFDIV_SHIFT 7 +#define IMXUART_UFCR_RFDIV_DIV6 (0 << 7) +#define IMXUART_UFCR_RFDIV_DIV5 (1 << 7) +#define IMXUART_UFCR_RFDIV_DIV4 (2 << 7) +#define IMXUART_UFCR_RFDIV_DIV3 (3 << 7) +#define IMXUART_UFCR_RFDIV_DIV2 (4 << 7) +#define IMXUART_UFCR_RFDIV_DIV1 (5 << 7) +#define IMXUART_UFCR_RFDIV_DIV7 (6 << 7) +#define IMXUART_UFCR_DCEDTE (1 << 6) +#define IMXUART_UFCR_RXTL_MASK 0x0000003f +#define IMXUART_UFCR_RXTL_SHIFT 0 + +#define IMXUART_USR1_REG 0x0094 /* UART Status Register 1 */ +#define IMXUART_USR1_PARITYERR (1 << 15) +#define IMXUART_USR1_RTSS (1 << 14) +#define IMXUART_USR1_TRDY (1 << 13) +#define IMXUART_USR1_RTSD (1 << 12) +#define IMXUART_USR1_ESCF (1 << 11) +#define IMXUART_USR1_FRAMERR (1 << 10) +#define IMXUART_USR1_RRDY (1 << 9) +#define IMXUART_USR1_AGTIM (1 << 8) +#define IMXUART_USR1_DTRD (1 << 7) +#define IMXUART_USR1_RXDS (1 << 6) +#define IMXUART_USR1_AIRINT (1 << 5) +#define IMXUART_USR1_AWAKE (1 << 4) +/* 6040 5008 XXX */ + +#define IMXUART_USR2_REG 0x0098 /* UART Status Register 2 */ +#define IMXUART_USR2_ADET (1 << 15) +#define IMXUART_USR2_TXFE (1 << 14) +#define IMXUART_USR2_DTRF (1 << 13) +#define IMXUART_USR2_IDLE (1 << 12) +#define IMXUART_USR2_ACST (1 << 11) +#define IMXUART_USR2_RIDELT (1 << 10) +#define IMXUART_USR2_RIIN (1 << 9) +#define IMXUART_USR2_IRINT (1 << 8) +#define IMXUART_USR2_WAKE (1 << 7) +#define IMXUART_USR2_DCDDELT (1 << 6) +#define IMXUART_USR2_DCDIN (1 << 5) +#define IMXUART_USR2_RTSF (1 << 4) +#define IMXUART_USR2_TXDC (1 << 3) +#define IMXUART_USR2_BRCD (1 << 2) +#define IMXUART_USR2_ORE (1 << 1) +#define IMXUART_USR2_RDR (1 << 0) + +#define IMXUART_UESC_REG 0x009c /* UART Escape Character Register */ +#define IMXUART_UESC_ESC_CHAR_MASK 0x000000ff + +#define IMXUART_UTIM_REG 0x00a0 /* UART Escape Timer Register */ +#define IMXUART_UTIM_TIM_MASK 0x00000fff + +#define IMXUART_UBIR_REG 0x00a4 /* UART BRM Incremental Register */ +#define IMXUART_UBIR_INC_MASK 0x0000ffff + +#define IMXUART_UBMR_REG 0x00a8 /* UART BRM Modulator Register */ +#define IMXUART_UBMR_MOD_MASK 0x0000ffff + +#define IMXUART_UBRC_REG 0x00ac /* UART Baud Rate Count Register */ +#define IMXUART_UBRC_BCNT_MASK 0x0000ffff + +#define IMXUART_ONEMS_REG 0x00b0 /* UART One Millisecond Register */ +#define IMXUART_ONEMS_ONEMS_MASK 0x00ffffff + +#define IMXUART_UTS_REG 0x00b4 /* UART Test Register */ +#define IMXUART_UTS_FRCPERR (1 << 13) +#define IMXUART_UTS_LOOP (1 << 12) +#define IMXUART_UTS_DBGEN (1 << 11) +#define IMXUART_UTS_LOOPIR (1 << 10) +#define IMXUART_UTS_RXDBG (1 << 9) +#define IMXUART_UTS_TXEMPTY (1 << 6) +#define IMXUART_UTS_RXEMPTY (1 << 5) +#define IMXUART_UTS_TXFULL (1 << 4) +#define IMXUART_UTS_RXFULL (1 << 3) +#define IMXUART_UTS_SOFTRST (1 << 0) + +#define REG(_r) IMXUART_ ## _r ## _REG +#define FLD(_r, _v) IMXUART_ ## _r ## _ ## _v + +#define GETREG(bas, reg) \ + bus_space_read_4((bas)->bst, (bas)->bsh, (reg)) +#define SETREG(bas, reg, value) \ + bus_space_write_4((bas)->bst, (bas)->bsh, (reg), (value)) + +#define CLR(_bas, _r, _b) \ + SETREG((_bas), (_r), GETREG((_bas), (_r)) & ~(_b)) +#define SET(_bas, _r, _b) \ + SETREG((_bas), (_r), GETREG((_bas), (_r)) | (_b)) +#define IS_SET(_bas, _r, _b) \ + ((GETREG((_bas), (_r)) & (_b)) ? 1 : 0) + +#define ENA(_bas, _r, _b) SET((_bas), REG(_r), FLD(_r, _b)) +#define DIS(_bas, _r, _b) CLR((_bas), REG(_r), FLD(_r, _b)) +#define IS(_bas, _r, _b) IS_SET((_bas), REG(_r), FLD(_r, _b)) + + +#endif /* _UART_DEV_IMX5XX_H */
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